Datasheet

2003 Apr 10 68
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Notes
1. In order to prevent digital noise interfering with the L3-bus communication, the rise and fall times should be as small
as possible.
2. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to
1
⁄
64fs
cycle.
3. C
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
4. After this period, the first clock pulse is generated.
5. To be suppressed by the input filter.
t
HD;DAT
data hold time 0 −−μs
t
SP
pulse width of spikes note 5 0 − 50 ns
C
L
load capacitance for each bus line −−400 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
handbook, full pagewidth
MGS756
WS
BCK
DATAO
DATAI
t
f
t
r
t
h(WS)
t
su(WS)
t
BCKH
t
BCKL
T
cy(BCK)
t
h(DATAO)
t
su(DATAI)
t
h(DATAI)
t
d(DATAO-BCK)
t
d(DATAO-WS)
Fig.20 I
2
S-bus interface timing.