Datasheet

2003 Apr 10 62
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
12.3.3 SPDIF INPUT
Table 81 Register address 59H
Table 82 Description of register bits (address 59H)
Table 83 Register address 5CH (left) and 5FH (right); note 1
Note
1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72.
Table 84 register addresses 5BH (left) and 5EH (right); note 1
Note
1. See for the description of the SPDI bit the corresponding SPDO bit description of Table 72.
BIT151413121110 9 8
Symbol −−−−−−−SPDO_STATUS
BIT7654321 0
Symbol −−−−−−B_ERR SPDIF_LOCK
BIT SYMBOL DESCRIPTION
15 to 9 − reserved
8 SPDO_STATUS SPDIF encoder output status. If this bit is logic 0 then the SPDIF encoder output is
enabled; if this bit is logic 1 then the SPDIF encoder output is disabled.
7to2 − reserved
1B_ERR Bit error detection. If this bit is logic 0 then there is no biphase error; if this bit is logic 1
then there is a biphase error.
0 SPDIF_LOCK SPDIF lock indicator. If this bit is logic 0 then the SPDIF decoder block is not in lock; if
this bit is logic 1 then the SPDIF decoder block is in lock.
BIT 151413121110 9 8
Symbol −−−−−−−−
BIT76543210
Symbol SPDI_
BIT39
SPDI_
BIT38
SPDI_
BIT37
SPDI_
BIT36
SPDI_
BIT35
SPDI_
BIT34
SPDI_
BIT33
SPDI_
BIT32
BIT 151413121110 9 8
Symbol SPDI_
BIT31
SPDI_
BIT30
SPDI_
BIT29
SPDI_
BIT28
SPDI_
BIT27
SPDI_
BIT26
SPDI_
BIT25
SPDI_
BIT24
BIT76543210
Symbol SPDI_
BIT23
SPDI_
BIT22
SPDI_
BIT21
SPDI_
BIT20
SPDI_
BIT19
SPDI_
BIT18
SPDI_
BIT17
SPDI_
BIT16