Datasheet

2003 Apr 10 61
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 78 Description of register bits (address 18H)
12.3.2 D
ECIMATOR
Table 79 Register address 28H
Table 80 Description of register bits (address 28H)
BIT SYMBOL DESCRIPTION
15 to 7 − reserved
6SDETR2 Silence detector channel 2 right. If this bit is logic 0 then there is no silence
detection for the right input of channel 2; if this bit is logic 1 then there is silence
detection for the right input of channel 2.
5SDETL2 Silence detector channel 2 left. If this bit is logic 0 then there is no silence
detection for the left input of channel 2; if this bit is logic 1 then there is silence
detection for the left input of channel 2.
4SDETR1 Silence detector channel 1 right. If this bit is logic 0 then there is no silence
detection for the right input of channel 1; if this bit is logic 1 then there is silence
detection for the right input of channel 1.
3SDETL1 Silence detector channel 1 left. If this bit is logic 0 then there is no silence
detection for the left input of channel 1; if this bit is logic 1 then there is silence
detection for the left input of channel 1.
2 MUTE_STATE_M Mute status interpolator. If this bit is logic 0 then the interpolator is not muted; if this
bit is logic 1 then the interpolator is muted.
1 MUTE_STATE_CH2 Mute status channel 2. If this bit is logic 0 then the interpolator channel 2 is not
muted; if this bit is logic 1 then the interpolator channel 2 is muted.
0 MUTE_STATE_CH1 Mute status channel 1. If this bit is logic 0 then the interpolator channel 1 is not
muted; if this bit is logic 1 then the interpolator channel 1 is muted.
BIT1514131211 10 9 8
Symbol −−−−− − − −
BIT76543 2 1 0
Symbol −−−−−MT_ADC_stat − OVERFLOW
BIT SYMBOL DESCRIPTION
15 to 3 − reserved
2MT_ADC_statMute status decimator. If this bit is logic 0 then the decimator is not muted; if this bit is
logic 1 then the decimator is muted.
1 − reserved
0OVERFLOWOverflow decimator. If this bit is logic 0 then there is no overflow in the decimator (digital
level above −1.16 dB.); if this bit is logic 1 then there is an overflow in the decimator.