Datasheet

2003 Apr 10 55
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
12.2.4 SPDIF INPUT SETTINGS
Table 65 Register address 30H
Table 66 Description of register bits (address 30H)
11 to 2 − reserved
1 DC_SKIP DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the
DC filter is disabled. The DC filter is at the output of the comb filter just before the
decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle
tones from the audio band). This DC offset must not be amplified in order to prevent
clipping.
0 HP_EN_DEC High-pass enable. If this bit is logic 0 then the high-pass is disabled; if this bit is logic 1
then the high-pass is enabled. The high-pass is a DC filter which is at the output of the
decimation filter (running at f
s
).
BIT 15 14 13 12 11 10 9 8
Symbol −−− − −− − −
Default 0 0 0 0 0 0 0 0
BIT765432 1 0
Symbol −−−PON_SPDI −−SLICER_SEL1 SLICER_SEL0
Default 0 0 0 1 0 0 0 0
BIT SYMBOL DESCRIPTION
15 to 5 − reserved
4 PON_SPDI Power control SPDIF input. If this bit is logic 0 then the SPDIF input is switched to
Power-down mode; if this bit is logic 1 then the SPDIF input is switched to power-on
mode.
3and2 − reserved
1 and 0 SLICER_SEL[1:0] SPDIF source select. Value to select an IEC 60958 input channel:
00 = IEC 60958 input from pin SPDIF0
01 = IEC 60958 input from pin SPDIF1
10 = IEC 60958 input from pin SPDIF2
11 = IEC 60958 input from pin SPDIF3
BIT SYMBOL DESCRIPTION