Datasheet

2003 Apr 10 54
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 61 Description of register bits (address 21H)
Table 62 ADC input amp PGA gain settings
Table 63 Register address 22H
Table 64 Description of register bits (address 22H)
BIT SYMBOL DESCRIPTION
15 MT_ADC Mute ADC. If this bit is logic 0 then the ADC is not muted; if this bit is logic 1 then
the ADC is muted.
14 to 12 − reserved
11 to 8 PGA_GAIN_CTRLL[3:0] PGA gain control left channel. Value to program the gain of the left input
amplifier. There are nine settings (see Table 62).
7to4 − reserved
3 to 0 PGA_GAIN_CTRLR[3:0] PGA gain control right channel. Value to program the gain of the right input
amplifier. There are nine settings (see Table 62).
PGA_GAIN_
CTRLL3
PGA_GAIN_
CTRLL2
PGA_GAIN_
CTRLL1
PGA_GAIN_
CTRLL0
GAIN (dB)
PGA_GAIN_
CTRLR3
PGA_GAIN_
CTRLR2
PGA_GAIN_
CTRLR1
PGA_GAIN_
CTRLR0
0000 0
0001 3
0010 6
0011 9
0100 12
0101 15
0110 18
0111 21
1000 24
BIT 15 14 13 12 11 10 9 8
Symbol −−−ADCPOL_INV −−− −
Default 0 0 0 0 0 0 0 0
BIT765 4 321 0
Symbol −−− − −−DC_SKIP HP_EN_DEC
Default 0 0 0 0 0 0 1 1
BIT SYMBOL DESCRIPTION
15 to 13 − reserved
12 ADCPOL_INV ADC polarity control. If this bit is logic 0 then the ADC input is not inverted; if this bit is
logic 1 then the ADC input is inverted.