Datasheet

2003 Apr 10 53
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 58 Description of register bits (address 20H)
Table 59 ADC volume control settings
Table 60 Register address 21H
BIT SYMBOL DESCRIPTION
15 to 8 MA_DECL[7:0] ADC volume setting left channel. Value to program the ADC gain setting for the left
channel. The range is from +24 to −63 dB and −∞ dB (see Table 59).
7to0 MA_DECR[7:0] ADC volume setting right channel. Value to program the ADC gain setting for the right
channel. The range is from +24 to −63 dB and −∞ dB (see Table 59).
MA_
DECL7
MA_
DECL6
MA_
DECL5
MA_
DECL4
MA_
DECL3
MA_
DECL2
MA_
DECL1
MA_
DECL0
GAIN (dB)
MA_
DECR7
MA_
DECR6
MA_
DECR5
MA_
DECR4
MA_
DECR3
MA_
DECR2
MA_
DECR1
MA_
DECR0
00110000+24.0
00101111+23.5
00101110+23.0
:::::::::
00000010+1.0
00000001+0.5
000000000
11111111−0.5
:::::::::
10000100−62.0
10000011−62.5
10000010−63.0
10000001−63.5
10000000−∞
BIT15 141312 11 10 9 8
Symbol MT_ADC −−−PGA_GAIN_
CTRLL3
PGA_GAIN_
CTRLL2
PGA_GAIN_
CTRLL1
PGA_GAIN_
CTRLL0
Default 0 0 0 0 0 0 0 0
BIT76543210
Symbol − −−−PGA_GAIN_
CTRLR3
PGA_GAIN_
CTRLR2
PGA_GAIN_
CTRLR1
PGA_GAIN_
CTRLR0
Default 0 0 0 0 0 0 0 0