Datasheet

2003 Apr 10 50
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 49 Mixer gain setting
Note
1. See Table 52.
Table 50 De-emphasis setting for the incoming signal
Table 51 Register address 14H
Table 52 Description of register bits (address 14H)
MIX
(1)
MIX_GAIN MIXER OUTPUT GAIN
1 0 DAC output gain is set to 0 dB and mixer signal output gain is set −6dB
1 1 DAC output gain and mixer signal output gain are set to 0 dB
DE2_2 DE2_1 DE2_0
FUNCTION
DE1_2 DE1_1 DE1_0
000 off
001 32kHz
010 44.1kHz
011 48kHz
100 96kHz
BIT151413 1211109 8
Symbol DA_POL_
INV
SEL_NS MIX_POS MIX DAC_CH2_
SEL1
DAC_CH2_
SEL0
DAC_CH1_
SEL1
DAC_CH1_
SEL0
Default010 0 1101
BIT765 4 3210
Symbol SILENCE SDET_ON SD_
VALUE1
SD_
VALUE0
BASS_SEL BYPASS OS_IN1 OS_IN0
Default000 0 0000
BIT SYMBOL DESCRIPTION
15 DA_POL_INV DAC polarity control. If this bit is logic 0 then the DAC output is not inverted; if this
bit is logic 1 then the DAC output is inverted.
14 SEL_NS Select noise shaper. If this bit is logic 0 then the third order noise shaper is
selected; if this bit is logic 1 then the fifth order noise shaper is selected.
13 MIX_POS Mixer position. Mixing is done before or after the sound processing unit (see
Table 53).
12 MIX Mixer. If this bit is logic 0 then the mixer is disabled; if this bit is logic 1 then the mixer
is enabled (see Tables 48, 49 and 53).
11 and
10
DAC_CH2_SEL[1:0] DAC channel 2 input selection. Value to select the input mode to channel 2 of the
interpolator (see Table 54).
9 and 8 DAC_CH1_SEL[1:0] DAC channel 1 input selection. Value to select the input mode to channel 1 of the
interpolator (see Table 54).