Datasheet

2003 Apr 10 49
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 46 Register address 13H
Table 47 Description of register bits (address 13H)
Table 48 DAC gain setting
Notes
1. See Table 52.
2. X = don’t care
BIT 151413121110 9 8
Symbol − MTM GS MIXGAIN MT2 DE2_2 DE2_1 DE2_0
Default 00001000
BIT76543210
Symbol MTNS1 MTNS0 WS_SEL DE_SW MT1 DE1_2 DE1_1 DE1_0
Default 00000000
BIT SYMBOL DESCRIPTION
15 - reserved
14 MTM Master mute. If this bit is logic 0 then there is no master mute or the master de-mute is in
progress; if this bit is logic 1 then the master mute is in progress or muted.
13 GS Gain select. See Table 48.
12 MIXGAIN Mixer gain select. See Tables 48 and 49.
11 MT2 Channel 2 mute. If this bit is logic 0 then channel 2 is not muted or the de-mute is in
progress; if this bit is logic 1 then channel 2 is muted or the muting is in progress.
10 to 8 DE2_[2:0] De-emphasis setting for channel 2. See Table 50.
7 and 6 MTNS[1:0] Interpolator mute. Selection:
00 = no mute
01 = if no WS signal is detected, the noise shaper of the interpolator mute
1x = the noise shaper of the interpolator mute
5 WS_SEL WS signal select. If this bit is logic 0 then WS_DET is selected for the WS detection; if
this bit is logic 1 then FPLL is selected for the WS detection.
4 DE_SW De-emphasis select. If this bit is logic 0 then SPDIF pre-emphasis information is
selected; if this bit is logic 1 then the de-emphasis setting is selected.
3MT1 Channel 1 mute. If this bit is logic 0 then channel 1 is not muted or the de-mute is in
progress; if this bit is logic 1 then channel 1 is muted or the muting is in progress.
2to0 DE1_[2:0] De-emphasis setting for channel 1. See Table 50.
GS MIX
(1)
MIX_GAIN DAC GAIN (dB)
0X
(2)
X
(2)
0
10 0 6
11 0 0
10 1 6
11 1 6