Datasheet

2003 Apr 10 47
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 42 Register address 12H
Table 43 Description of register bits (address 12H)
10111100−48
11000000−50
:::::::::
11010100−60
11011000−63
11011100−66
11100000−72
11100100−∞
:::::::::
11111100−∞
BIT 151413121110 9 8
Symbol M1 M0 TRL1 TRL0 BBL3 BBL2 BBL1 BBL0
Default 00000000
BIT76543210
Symbol BB_OFF BB_FIX TRR1 TRR0 BBR3 BBR2 BBR1 BBR0
Default 00000000
BIT SYMBOL DESCRIPTION
15 and 14 M[1:0] Sound feature mode. Value to program the sound processing filter sets (modes) of bass
boost and treble:
00 = flat set
01 = minimum set
10 = minimum set
11 = maximum set
13 and 12 TRL[1:0] Treble settings left. Value to program the left channel treble setting. Both left and right
channels will follow the left channel setting when bit BASS_SEL = 1. The used filter set is
selected with the sound feature mode bits M1 and M2 (see Table 44).
11 to 8 BBL[3:0] Normal bass boost settings left. Value to program the left bass boost settings. The
used filter set is selected by the sound feature mode bits M1 and M2 (see Table 45).
7 BB_OFF Resonant bass boost. If this bit is logic 0 then the resonant bass boost is enabled; if this
bit is logic 1 then the resonant bass boost is disabled.
VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0
VOLUME (dB)
VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0