Datasheet

2003 Apr 10 46
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 39 Register address 11H
Table 40 Description of register bits (address 11H)
Table 41 Mixer volume setting channel 1 and 2
11010100−54
11011000−56
:::::::::
11101100−66
11110000−69
11110100−72
11111000−78
11111100−∞
BIT151413121110 9 8
Symbol VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0
Default11111111
BIT76543210
Symbol VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0
Default00000000
BIT SYMBOL DESCRIPTION
15 to 8 VC2_[7:0] Mixer volume setting channel 2. Value to program channel 2 mixer volume attenuation. The
range is 0 dB to −72 dB and ∞ dB (see Table 41).
7to0 VC1_[7:0] Mixer volume setting channel 1. Value to program channel 1 mixer volume attenuation. The
range is 0 dB to −72 dB and ∞ dB (see Table 41).
VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0
VOLUME (dB)
VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0
000000000
00000001−0.25
00000010−0.5
00000011−0.75
00000100−1
:::::::::
10110100−45
10110101−45.25
10110110−45.5
10110111−45.75
10111000−46
MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0
VOLUME (dB)
MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0