Datasheet

2003 Apr 10 45
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 35 ADC power control
12.2.2 I
NTERPOLATOR
Table 36 Register address 10H
Table 37 Description of register bits (address 10H)
Table 38 Master volume setting left and right channel
PON_ADC_BIAS PON_ADCR PON_ADCL DESCRIPTION
0 X X no power on both ADCs
1 0 0 no power on both ADCs
1 1 0 only power on right channel ADC
1 0 1 only power on left channel ADC
1 1 1 power on both ADCs
BIT15 1413121110 9 8
Symbol MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0
Default0 0000000
BIT7 6543210
Symbol MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0
Default0 0000000
BIT SYMBOL DESCRIPTION
15 to 8 MVCL_[7:0] Master volume setting left channel. Value to program the left channel master volume
attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38).
7to0 MVCR_[7:0] Master volume setting right channel. Value to program the right channel master volume
attenuation. The range is 0 dB to −78 dB and ∞ dB (see Table 38).
MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0
VOLUME (dB)
MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0
000000000
00000001−0.25
00000010−0.5
00000011−0.75
00000100−1
:::::::::
11001100−51
11001101−51.25
11001110−51.5
11001111−51.75
11010000−52