Datasheet

2003 Apr 10 44
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 33 Register address 04H
Table 34 Description of register bits (address 04H)
2 to 0 SFORI[2:0] Digital input format. Value to set the digital input format:
000 = I
2
S-bus
001 = LSB-justified; 16 bits
010 = LSB-justified; 18 bits
011 = LSB-justified; 20 bits
100 = LSB-justified; 24 bits
101 = MSB-justified
110 = not used; input is default value
111 = not used; input is default value
BIT 15 14 13 12 11 10 9 8
Symbol PON_DAC −−−−PON_ADCL PON_ADCR PON_ADC_bias
Default 1 0 0 0 0 1 1 1
BIT
7 6 543 2 1
0
Symbol DACLK_OFF DACLK_AUTO −−−EN_DEC − EN_INT
Default 0 0 0 0 0 1 0 1
BIT SYMBOL DESCRIPTION
15 PON_DAC Power control DAC. If this bit is logic 0, then the DAC is in Power-down mode; if this bit
is logic 1, then the DAC is in power-on mode. This bit is only connected to the DAC input
and is not combined with mute status or other signals.
14 to 11 − reserved
10 PON_ADCL Power control ADC left channel. Value to set power on the ADC left channel (see
Table 35).
9PON_ADCR Power control ADC right channel. Value to set power on the ADC right channel (see
Table 35).
8PON_ADC_biasPower control ADC bias. Value to set power on the ADCs (see Table 35).
7DACLK_OFF DAC clock enable. If this bit is logic 0, then the DAC clock is disabled; if this bit is
logic 1, then the DAC clock is enabled.
6DACLK_AUTODAC clock auto function. If this bit is logic 0, then the DAC clock auto function is
disabled; if this bit is logic 1, then the DAC clock auto function is enabled. If the FPLL is
unlocked, the interpolator will be muted and the DAC clock is automatically disabled.
5to3 − reserved
2 EN_DEC Decimator and ADC clock enable. If this bit is logic 0, then the clock to decimator and
ADC is disabled; if this bit is logic 1, then the clock to decimator and ADC is running.
1 − reserved
0EN_INT Interpolator clock enable. If this bit is logic 0, then the clock to interpolator and FSDAC
is disabled; if this bit is logic 1, then the clock to the interpolator and FSDAC is running.
BIT SYMBOL DESCRIPTION