Datasheet

2003 Apr 10 40
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
12.2 Read/write registers mapping
12.2.1 S
YSTEM SETTINGS
Table 25 Register address 00H
5DH R SPDIF input status bits 15 to 0 right channel read-out
5EH R SPDIF input status bits 31 to 16 right channel read-out
5FH R SPDIF input status bits 39 to 32 right channel read-out
SPDIF output
50H R/W SPDIF output valid; left to right channel status bit copy; power control and SPDIF output
selection setting
51H R/W SPDIF output status bits 39 to 24 left channel setting
52H R/W SPDIF output status bits 23 to 8 left channel setting
53H R/W SPDIF output status bits 7 to 0 left channel setting
54H R/W SPDIF output status bits 39 to 24 right channel setting
55H R/W SPDIF output status bits 23 to 8 right channel setting
56H R/W SPDIF output status bits 7 to 0 right channel setting
60H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
61H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
62H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
63H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
64H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
Device ID
7EH R device ID; version
Software reset
7FH R/W restore L3-bus defaults
BIT 15 14 13 12 11 10 9 8
Symbol EXPU − PON_XTAL
PLL
XTL_DIV4 XTL_DIV3 XTL_DIV2 XTL_DIV1 XTL_DIV0
Default 0 0 1 0 1 0 0 0
BIT 7 6 5 4 3 2 1 0
Symbol MODE3 MODE2 MODE1 MODE0 ws_detct_EN ws_detct_set CLKOUT_
SEL1
CLKOUT_
SEL0
Default 0 0 1 0 1 0 1 0
ADDRESS R/W DESCRIPTION