Datasheet

2003 Apr 10 39
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
12 REGISTER MAPPING
In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the
mapping of the readable and writable registers is given. The explanation of the register definitions are explained in
Sections 12.2 and 12.3.
12.1 Address mapping
Table 24 Register map settings
ADDRESS R/W DESCRIPTION
System settings
00H R/W crystal clock power-on setting; crystal clock and PLL divider settings; MODE and WS detector
settings; clock output setting
01H R/W I
2
S-bus output format settings
02H R/W I
2
S-bus input format settings
03H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
04H R/W analog power and clock settings
Interpolator
10H R/W master volume control settings
11H R/W mixer volume settings
12H R/W sound feature and bass boost and treble settings
13H R/W gain select; de-emphasis and mute settings
14H R/W DAC polarity; noise shaper selection; mixer; source selection; silence detector and interpolator
oversampling settings
18H R mute and silence detector status read-out
19H R/W resonant bass boost coefficient k1 setting
1AH R/W resonant bass boost coefficient km setting
1BH R/W resonant bass boost coefficient a1 setting
1CH R/W resonant bass boost coefficient a2 setting
1DH R/W resonant bass boost coefficient b1 setting
1EH R/W resonant bass boost coefficient b2m setting
Decimator
20H R/W ADC gain settings
21H R/W ADC mute and PGA gain settings;
22H R/W ADC polarity and DC cancellation settings
28H R mute status and overflow ADC read-out
SPDIF input
30H R/W SPDIF power control and SPDIF input settings
40H R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
59H R SPDIF LOCK; bit error information and SPDIF encoder output status read-out
5AH R SPDIF input status bits 15 to 0 left channel read-out
5BH R SPDIF input status bits 31 to 16 left channel read-out
5CH R SPDIF input status bits 39 to 32 left channel read-out