Datasheet

2003 Apr 10 32
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 15 Preambles
9.3 Timing characteristics
9.3.1 F
REQUENCY REQUIREMENTS
The SPDIF specification IEC 60958 supports three levels
of clock accuracy:
• Level I high accuracy: Tolerance of transmitting
sampling frequency shall be within 50 × 10
−6
• Level II, normal accuracy: All receivers should receive a
signal of 1000 × 10
−6
of nominal sampling frequency
• Level III, variable pitch shifted clock mode: A deviation
of 12.5% of the nominal sampling frequency is possible.
The UDA1355H inputs support level I, II, and III as
specified by the IEC 60958 standard.
9.3.2 R
ISE AND FALL TIMES
Rise and fall times (see Fig.14) are defined as:
Rise time =
Fall time =
Rise and fall times should be in the range:
• 0% to 20% when the data bit is a logic 1
• 0% to 10% when the data bits are two succeeding
logic 0.
9.3.3 D
UTY CYCLE
The duty cycle (see Fig.14) is defined as:
Duty cycle =
The duty cycle should be in the range:
• 40% to 60% when the data bit is a logic 1
• 45% to 55% when the data bits are two succeeding
logic 0.
10 L3-BUS DESCRIPTION
The exchange of data and control information between the
microcontroller and the UDA1355H is accomplished
through a serial hardware L3-bus interface comprising the
following pins:
• MP0: mode line with signal L3MODE
• MP1: clock line with signal L3CLOCK
• MP2: data line with signal L3DATA.
The exchange of bytes in L3-bus mode is LSB first.
The L3-bus format has two modes of operation:
• Address mode
• Data transfer mode.
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see
Fig.15). The data transfer mode is characterized by
L3MODE being HIGH and is used to transfer one or more
bytes representing a register address, instruction or data.
Basically two types of data transfers can be defined:
• Write action: data transfer to the device
• Read action: data transfer from the device.
10.1 Device addressing
The device address consists of one byte with:
• Data Operating Mode (DOM) bits 0 and 1 representing
the type of data transfer (see Table 16)
• Address bits 2 to 7 representing a 6-bit device address.
PRECEDING
STATE
CHANNEL CODING
01
B 1110 1000 0001 0111
M 11100010 00011101
W 11100100 00011011
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handbook, halfpage
90%
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MGU612
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Fig.14 Rise, fall time and duty cycle.
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