Datasheet

2003 Apr 10 20
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Note
1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode.
8.2 Static mode basic applications
The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level
pin. In Table 10, the encoding of the pins MODE[2:0] is given.
Table 10 Static mode basic applications
Notes
1. In column mode selection pins means:
L: pin at 0 V; M: pin at half V
DDD
; H: pin at V
DDD
.
2. In column clock means:
xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL.
30, 31 SFOR1, SFOR0 LOW, LOW set I
2
S-bus format for digital data input and output interface
LOW, HIGH set LSB-justified 16 bits format for digital data input interface and
MSB-justified format for digital data output interface
HIGH, LOW set LSB-justified 24 bits format for digital data input interface and
MSB-justified format for digital data output interface
HIGH, HIGH set MSB-justified format for digital data input and output interface
44 MUTE LOW normal operation
HIGH mute active
MODE
MODE SELECTION PINS
(1)
CLOCK
(2)
PLL
LOCKS
ON
INPUT
SPDIF
INPUT
SPDIF
OUTPUT
ADC DAC
I
2
S-BUS
INPUT
SLAVE
I
2
S-BUS
OUTPUT
MASTER
MODE2 MODE1 MODE0
0L L LPLLPLL− PLL − PLL SPDIF
1L L M − PLL − PLL PLL − I
2
S-bus
2L L HPLLPLL− PLL PLL PLL SPDIF
3L H L − xtal xtal −−xtal −
4L H M − xtal xtal xtal xtal xtal −
5L H H − xtal xtal xtal xtal xtal −
6H L L − PLL xtal PLL PLL xtal I
2
S-bus
7 H L M PLL xtal xtal PLL − xtal SPDIF
8H L H − xtal xtal PLL PLL xtal I
2
S-bus
9H H LPLLxtal − xtal xtal PLL SPDIF
10 H H M PLL xtal − PLL xtal PLL SPDIF
11 H H H not used
PIN
STATIC MODE
SYMBOL
LEVEL DESCRIPTION