Datasheet

2003 Apr 10 18
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
Table 8 Muting to prevent plopping
OCCASION
BIT
DE-MUTE CONDITION
MT1 MT2 MTM
Input selection
Select channel 1 source x −−no mute after selection
Select channel 2 source − x − no mute after selection
Select chip mode
PLL is source for the DAC −−x wait until PLL is locked again
Crystal is source for the DAC −−x no mute after selection
Select between microcontroller mode and static mode
PLL is source for the DAC −−x wait until PLL is locked again
Crystal is source for the DAC −−x no mute after selection
Audio features
Select noise shaper order −−x no mute after selection
Select FSDAC output polarity −−x no mute after selection
Select SPDIF input −−x PLL is locked again
Select mixer −−−no mute needed
Select mixer position −−−no mute needed
Select crystal clock source −−x no mute after selection
7.8 Digital audio input and output
The selection of the digital audio input and output formats
and master or slave modes differ for static and
microcontroller mode.
In master mode, when 256f
s
output clock is selected and
the digital interface is master, the BCK output clock will be
64f
s
. In case 384f
s
output clock is selected, the BCK output
clock will be 48f
s
.
In the static mode the digital audio input formats are:
• I
2
S-bus
• LSB-justified; 16 bits
• LSB-justified; 24 bits
• MSB-justified.
The digital audio output formats are:
• I
2
S-bus
• MSB-justified.
In the microcontroller mode, the following formats are
independently selectable:
• I
2
S-bus
• LSB-justified; 16 bits
• LSB-justified; 18 bits
• LSB-justified; 20 bits
• LSB-justified; 24 bits
• MSB-justified.
7.9 Power-on reset
The UDA1355H has a dedicated reset pin with an internal
pull-down resistor. In this way a Power-on reset circuit can
be made with a capacitor and a resistor at pin RESET. The
external resistor is needed since the pad is 5 V tolerant.
This means that there is a transmission gate in series with
the input and the resistor inside the pad cannot be seen
from the outside world (see Fig.10).
The reset timing is determined by the external pull-down
resistor and the external capacitor which is connected to
pin RESET. At Power-on reset, all the digital sound
processing features and the system controlling features
are set to the default setting of the microcontroller mode.
Since the bit controlling the clock of the synchronous
registers is set to enable, the synchronous registers are
also reset.