Datasheet

2003 Apr 10 12
NXP Semiconductors Preliminary specification
Stereo audio codec with SPDIF interface UDA1355H
7.3.2 PLL CLOCK SYSTEM
The PLL locks on the incoming digital data of the SPDIF or
WS input signal. The PLL recovers the clock from the
SPDIF or WSI signal and removes jitter to produce a stable
system clock (see Fig.4).
7.3.3 W
ORD SELECTION DETECTION CIRCUIT
This circuit is clocked by the 12.288 MHz crystal oscillator
clock and generates a Word Selection (WS) detection
signal. If the WS detector does not detect any WS edge,
defined as 7 times LOW and 7 times HIGH, then the
WS detection signal is LOW. This information can be used
to set the clock for the noise shaper in the interpolator. This
will prevent noise shaper noise in the audio band.
7.3.4 C
LOCK OUTPUT
The UDA1355H has a clock output pin (pin CLK_OUT),
which can be used to drive other audio devices in the
system. In microcontroller mode the output clock is
256f
s
or 384f
s
. In static mode the output clock is 256 times
32, 44.1 and 48 kHz.
The source of the output clock is either the crystal
oscillator or the PLL, depending on the selected
application and control mode.
7.4 IEC 60958 decoder
The UDA1355H IEC 60958 decoder can select one of four
SPDIF input channels. An on-chip amplifier with hysteresis
amplifies the SPDIF input signal to CMOS level, making it
possible to accept both analog and digital SPDIF signals
(see Fig.5).
7.4.1 A
UDIO DATA
From the incoming SPDIF bitstream 24 bits of data for the
left and right channel are extracted.
There is a hard mute (not a cosine roll-off mute) if the
IEC 60958 decoder is out of lock or detects bi-mark phase
encoding violations. The lock indicator and the key
channel status bits are accessible in L3-bus mode.
The UDA1355H supports the following sample
frequencies and data rates, including half and double of
these frequencies:
• f
s
= 32 kHz; resulting in a data rate of 2.048 Mbit/s
• f
s
= 44.1 kHz; resulting in a data rate of 2.8224 Mbit/s
• f
s
= 48 kHz; resulting in a data rate of 3.072 Mbit/s.
handbook, halfpage
MGU830
13
XTALIN
XTALOUT
CLK_OUT
12.288 MHz
14
11
UDA1355H
CRYSTAL
OSCILLATOR
PLL
MODULE
256f
s
or 384f
s
clock
L3-bus or I
2
C-bus
register setting
PLL clock
Fig.3 Crystal oscillator clock system.
MGU827
SLICER
23
24
25
26
2
SPDIF0
SPDIF1
SPDIF2
SPDIF3
WSI
UDA1355H
IEC 60958
DECODER
PLL
select SPDIF source
256f
s
or
384f
s
Fig.4 PLL clock system.
handbook, halfpage
MGU829
23
24
25
26
SPDIF0
SPDIF1
SPDIF2
SPDIF3
75 Ω
180 pF
10 nF
UDA1355H
Fig.5 IEC 60958 input circuit.