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DATA SHEET

Preliminary specification 2003 Apr 10

INTEGRATED CIRCUITS

UDA1355H

Stereo audio codec with SPDIF

interface

Summary of content (76 pages)

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INTEGRATED CIRCUITS DATA SHEET UDA1355H Stereo audio codec with SPDIF interface Preliminary specification 2003 Apr 10
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface CONTENTS UDA1355H 11 I2C-BUS DESCRIPTION Characteristics Bit transfer Byte transfer Data transfer Register address Device address Start and stop conditions Acknowledgment Write cycle Read cycle 1 FEATURES 1.1 1.2 1.3 1.4 1.5 1.6 1.7 General Control IEC 60958 input IEC 60958 output Digital I/O interface ADC digital sound processing DAC digital sound processing 2 GENERAL DESCRIPTION 11.1 11.2 11.3 11.4 11.5 11.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 1 1.1 UDA1355H FEATURES General • 2.7 to 3.6 V power supply • Integrated digital interpolator filter and Digital-to-Analog Converter (DAC) • 24-bit data path in interpolator • No analog post filtering required for DAC • Integrated Analog-to-Digital Converter (ADC), Programmable Gain Amplifier (PGA) and digital decimator filter • 32, 44.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface • Programmable digital silence detector which can generate level II output signals with CMOS levels. In microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the IC, offering a flexible analog, digital and SPDIF converter chip with possibilities for off-chip sound processing via the digital input and output interface.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 4 UDA1355H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA1 DAC supply voltage 2.7 3.0 3.6 V VDDA2 ADC supply voltage 2.7 3.0 3.6 V VDDX crystal oscillator and PLL supply voltage 2.7 3.0 3.6 V VDDI digital core supply voltage 2.7 3.0 3.6 V VDDE digital pad supply voltage IDDA1 DAC supply current IDDA2 ADC supply current 2.7 3.0 3.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER CONDITIONS UDA1355H MIN. TYP. MAX. UNIT Analog-to-digital converter; fi = 1 kHz; VDDA2 = 3.0 V Vi(rms) input voltage (RMS value) ΔVi input voltage unbalance (THD+N)/S total harmonic distortion-plus-noise to signal ratio Vo = −1.16 dBFS digital output − 1.0 − V − 0.
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RTCB WSI DATAI BCKI SPDIF0 7 SPDIF1 SPDIF2 SPDIF3 SLICER_SEL0 SLICER_SEL1 LOCK 37 27 38 11 VDDE VDDA1 6 39 13 14 34 36 CLOCK AND TIMING XTAL ADC COMB FILTER AUDIO FEATURE PROCESSOR AUDIO FEATURE PROCESSOR DECIMATOR ADC DAC INTERPOLATOR NOISE SHAPER DAC 40 42 44 16 43 INPUT AND OUTPUT SELECT 2 3 DATA IN 9 8 DATA OUT 10 1 VOUTL VOUTR MUTE WSO DATAO BCKO SLICER 23 24 IEC 60958 DECODER 25 IEC 60958 ENCODER 26 5 NXP Semiconductors RESET 32 VREF Stereo audio codec
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 6 UDA1355H PINNING SYMBOL PIN PAD(1) DESCRIPTION BCKI 1 bpt4mtht5v bit clock input (master or slave) WSI 2 bpt4mtht5v word select input (master or slave) DATAI 3 iptht5v digital data input LOCK 4 op4mc PLL lock indicator output SPDIFOUT 5 op4mc SPDIF output VDDE 6 vdde digital pad supply voltage VSSE 7 vsse digital pad ground DATAO 8 ops5c digital data output WSO 9 bpt4mtht5v word
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL VINL PIN 34 PAD(1) apio UDA1355H DESCRIPTION ADC left channel input VSSA2 35 vssco ADC ground VINR 36 apio ADC right channel input VDDA2 37 vddco ADC supply voltage VREF 38 apio reference voltage for ADC and DAC VDDA1 39 vddco DAC supply voltage VOUTL 40 apio DAC left channel output VSSA1 41 vssco DAC ground VOUTR 42 apio DAC right channel output RTCB 43 ipthdt5v test contro
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NXP Semiconductors Preliminary specification 34 VINL 36 VINR 35 VSSA2 UDA1355H 37 VDDA2 38 VREF 39 VDDA1 40 VOUTL 41 VSSA1 42 VOUTR 44 MUTE handbook, full pagewidth 43 RTCB Stereo audio codec with SPDIF interface BCKI 1 33 VADCN WSI 2 32 VADCP DATAI 3 31 MP2 LOCK 4 30 MP1 SPDIFOUT 5 29 MP0 VDDE 6 28 VSSIS UDA1355H 27 VDDI VSSE 7 SLICER_SEL1 22 SEL_STATIC 20 SLICER_SEL0 21 MODE2 19 MODE1 18 MODE0 17 23 SPDIF0 RESET 16 24 SPDIF1 VSSX 15 BCKO 10 CLK_OUT 11 XTALOUT 14
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface • Set two times 40 bits of channel status bits of the SPDIF output UDA1355H Table 3 Output frequencies OUTPUT FREQUENCY • Select one of four SPDIF input sources BASIC AUDIO FREQUENCY • Enable digital mixer inside interpolator • Control mute and mixer volumes of digital mixer • Selection of filter mode and settings of treble and bass boost for the interpolator (DAC) section 32 kHz MICROCONTROLLER MODE 256 × 16 kHz
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 7.3.4 The UDA1355H has a clock output pin (pin CLK_OUT), which can be used to drive other audio devices in the system. In microcontroller mode the output clock is 256fs or 384fs. In static mode the output clock is 256 times 32, 44.1 and 48 kHz. 12.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 7.4.2 CHANNEL STATUS AND USER BITS 7.5 As well as the data bits there are several IEC 60958 key channel status bits: UDA1355H IEC 60958 encoder When using the crystal oscillator clock, the IEC 60958 encoder output is a full-swing digital signal with level II timing. • Pre-emphasis and audio sampling frequency bits • Two channel PCM indicator bits • Clock accuracy bits.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface handbook, full pagewidth SPDOUT_SEL1 UDA1355H SPDOUT_SEL0 SPDIF0 SPDIF1 SPDIF2 SPDIF3 23 UDA1355H SPDOUT_SEL2 MODE [3:0] IEC 60958 DECODER 24 25 26 5 SLICER SPDIF OUT select SPDIF source SPDIF source IEC 60958 ENCODER 21, 22 17 to 19 SLICER_SEL [1:0] 20 MODE [2:0] SEL_STATIC MGU833 Fig.6 Selection options for SPDIF output. 7.6 Analog input 7.6.1 7.6.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 7.6.3 • Support for 1fs and 2fs input data rate and 192 kHz audio via I2S-bus. DC FILTERING In the decimator there are two digital DC blocking circuits. The stereo interpolator has the following sound features: The first blocking circuit is in front of the volume control to remove DC bias from the ADC output. The DC bias is added in the ADC to prevent audio band Idle tones occurring in the noise shaper.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 7 Interpolation filter characteristics ITEM CONDITIONS VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.035 >0.55fs −60 0 to 0.4535fs 140 Stop band Dynamic range 7.7.3 mute controls available: for source 1, for source 2 and for the master (sum) signal. All three volume ranges can be controlled in 0.25 dB steps.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth DE-EMPHASIS mixing after sound features mixing before sound features channel 2 VOLUME AND MUTE 1fs UDA1355H L3/I2C bit DE-EMPHASIS VOLUME AND MUTE BASS-BOOST AND TREBLE INT. FILTER 2fs channel 1 MASTER VOLUME AND MUTE to interpolation filter and DAC output output of mixer MGU834 Fig.9 Digital mixer (DAC) inside the interpolator DSP. 7.7.4 DIGITAL SILENCE DETECTOR 7.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 8 UDA1355H Muting to prevent plopping BIT OCCASION DE-MUTE CONDITION MT1 MT2 MTM Select channel 1 source x − − no mute after selection Select channel 2 source − x − no mute after selection PLL is source for the DAC − − x wait until PLL is locked again Crystal is source for the DAC − − x no mute after selection Input selection Select chip mode Select between microcontroller mode and static
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8 handbook, halfpage RESET APPLICATION MODES In this chapter the application modes for static mode and microcontroller mode are described. Transmission gate for 5V tolerance The UDA1355H can be controlled by static pins, the L3-bus or I2C-bus interface. Due to the limitations imposed by the pin count, only basic functions are available in static mode.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface STATIC MODE SYMBOL PIN 30, 31 44 UDA1355H LEVEL SFOR1, SFOR0 DESCRIPTION LOW, LOW set I2S-bus format for digital data input and output interface LOW, HIGH set LSB-justified 16 bits format for digital data input interface and MSB-justified format for digital data output interface HIGH, LOW set LSB-justified 24 bits format for digital data input interface and MSB-justified format for digital data output interfa
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H The first 11 application modes are given in this section. Schematic diagrams of these application modes are given in Table 11. In this table the basic features are mentioned and also the extra features in case of microcontroller mode are given. It should be noted that the blocks running at the crystal clock (XTAL) are marked unshaded while the blocks running at the PLL clock are shaded.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 2 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to outputs I2S or SPDIFOUT via loop through • Input I2S to output DAC.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 5 UDA1355H FEATURES SCHEMATIC Data path: • Input ADC to outputs I2S or SPDIF • Input I2S to output DAC. XTAL Features: MUTE • Possibility to process input ADC via I2S-bus using an external DSP and then to output DAC ADC DAC SPDIF OUT • Crystal oscillator generates the clocks I2S INPUT • I2S input and output with BCK and WS are master I 2S OUTPUT I 2S slave • Microcontroller mode: see Section 8.4.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 7 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to output DAC • Input ADC to outputs SPDIF or I2S.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 9 UDA1355H FEATURES SCHEMATIC Data path: • Input SPDIF to output I2S • Input I2S to outputs DAC or SPDIF.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8.3 UDA1355H Microcontroller mode pin assignment In microcontroller mode all features become available, such as volume control, PGA gain and mixing (in some modes). The pin functions are defined in Table 12.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 8.4 UDA1355H Microcontroller mode applications In Table 13, the encoding of bits MODE[3:0] in the microcontroller mode is given.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H In the microcontroller mode, more features are available. The application modes are given in Table 14. Some modes are the same in terms of data path as for the static mode. These modes are already explained in Section 8.2. Some modes are combined into one mode (like modes 4 and 5).
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE UDA1355H FEATURE 6 See static mode 7 See static mode 8 See static mode 9 Data path: SCHEMATIC • Inputs ADC and I2S to outputs DAC or SPDIF • Input SPDIF to output I2S.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface MODE 12 UDA1355H FEATURE SCHEMATIC Data path: • Input ADC to outputs I2S or SPDIF • Inputs I2S and SPDIF to output DAC.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 9 9.1 SPDIF SIGNAL FORMAT 9.2 SPDIF channel encoding UDA1355H SPDIF hierarchical layers The SPDIF signal format is shown in Fig.12. A PCM signal is transmitted in sequential blocks. Each block consists of 192 frames. Each frame contains two sub-frames, one for each channel. Each subframe is preceded by a preamble. There are three types of preambles: B, M and W.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 15 Preambles 9.3.3 PRECEDING STATE 9.3 9.3.1 UDA1355H DUTY CYCLE CHANNEL CODING The duty cycle (see Fig.14) is defined as: 0 tH Duty cycle = --------------- × 100% tL + tH 1 B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 The duty cycle should be in the range: • 40% to 60% when the data bit is a logic 1 • 45% to 55% when the data bits are two succeeding logic 0.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Table 16 Selection of data transfer 10.
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L3CLOCK L3MODE device address 1 0 L3DATA register address data byte 1 data byte 2 0 MGS753 DOM bits write Fig.15 Data write mode. NXP Semiconductors Stereo audio codec with SPDIF interface 2003 Apr 10 L3 wake-up pulse after power-up 34 L3CLOCK L3MODE register address device address L3DATA 1 DOM bits read 1 1 register address data byte 1 data byte 2 0/1 valid/non-valid send by the device Fig.16 Data read mode.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 18 L3-bus write data FIRST IN TIME BYTE L3-BUS MODE LAST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 A0 1 0 0 0 0 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 19 L3-bus read data FIRST
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 11.3 Byte transfer 11.7 Each byte (8 bits) is transferred with the MSB first (see Table 20). 7 11.4 BIT 6 5 4 LSB 3 2 1 0 11.8 A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.19 Acknowledge on the I2C-bus. 11.9 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1355H must start.
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The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1355H. 4. After this microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1355H must start. 5. The UDA1355H acknowledges this register address (A). 6.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 12 REGISTER MAPPING In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the mapping of the readable and writable registers is given. The explanation of the register definitions are explained in Sections 12.2 and 12.3. 12.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface ADDRESS R/W UDA1355H DESCRIPTION 5DH R SPDIF input status bits 15 to 0 right channel read-out 5EH R SPDIF input status bits 31 to 16 right channel read-out 5FH R SPDIF input status bits 39 to 32 right channel read-out SPDIF output 50H R/W SPDIF output valid; left to right channel status bit copy; power control and SPDIF output selection setting 51H R/W SPDIF output status bits 39 to 24 left channel sett
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 26 Description of register bits (address 00H) BIT SYMBOL DESCRIPTION 15 EXPU EXPU. Bit EXPU is reserved for manufacturers evaluation and should be kept untouched for normal operation of UDA1355H. 14 − reserved 13 PON_XTALPLL Power control crystal oscillator and PLL.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface XTL_DIV4 XTL_DIV3 XTL_DIV2 XTL_DIV1 UDA1355H XTL_DIV0 OUTPUT RATE Based on 48 kHz 0 1 1 0 0 256 × 24 kHz 0 1 1 0 1 384 × 24 kHz 0 1 1 1 0 256 × 48 kHz 0 1 1 1 1 384 × 48 kHz 1 0 0 0 0 256 × 96 kHz 1 0 0 0 1 384 × 96 kHz Table 28 Application mode selection MODE3 MODE2 MODE1 MODE0 FUNCTION 0 0 0 0 mode 0 0 0 0 1 mode 1 0 0 1 0 mode 2 0 0 1 1 mode 3 0 1 0
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 30 Description of register bits (address 01H) BIT SYMBOL DESCRIPTION − reserved 8 MUTE_DAO Digital mute setting. If this bit is logic 0, then the digital output is not muted; if this bit is logic 1, then the digital output is muted. 7 PON_DIGO Power control digital output.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT 2 to 0 SYMBOL SFORI[2:0] UDA1355H DESCRIPTION Digital input format.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 35 ADC power control PON_ADC_BIAS PON_ADCR PON_ADCL 0 X X no power on both ADCs 1 0 0 no power on both ADCs 12.2.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H MVCL_7 MVCL_6 MVCL_5 MVCL_4 MVCL_3 MVCL_2 MVCL_1 MVCL_0 MVCR_7 MVCR_6 MVCR_5 MVCR_4 MVCR_3 MVCR_2 MVCR_1 MVCR_0 1 1 0 1 0 1 0 0 −54 1 1 0 1 1 0 0 0 −56 : : : : : : : : : 1 1 1 0 1 1 0 0 −66 1 1 1 1 0 0 0 0 −69 1 1 1 1 0 1 0 0 −72 1 1 1 1 1 0 0 0 −78 1 1 1 1 1 1 0 0 −∞ VOLUME (dB) Table 39 Register address 11H BIT 15 14 1
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H VC2_7 VC2_6 VC2_5 VC2_4 VC2_3 VC2_2 VC2_1 VC2_0 VC1_7 VC1_6 VC1_5 VC1_4 VC1_3 VC1_2 VC1_1 VC1_0 VOLUME (dB) 1 0 1 1 1 1 0 0 −48 1 1 0 0 0 0 0 0 −50 : : : : : : : : : 1 1 0 1 0 1 0 0 −60 1 1 0 1 1 0 0 0 −63 1 1 0 1 1 1 0 0 −66 1 1 1 0 0 0 0 0 −72 1 1 1 0 0 1 0 0 −∞ : : : : : : : : : 1 1 1 1 1 1 0 0 −∞ Table
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL UDA1355H DESCRIPTION 6 BB_FIX Resonant bass boost coefficient. If this bit is logic 0 then the resonant bass boost coefficient is finished loading; if this bit is logic 1 then the resonant bass boost coefficient is loading to register. 5 and 4 TRR[1:0] Treble settings right. Value to program the right treble setting.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 46 Register address 13H BIT 15 14 13 12 11 10 9 8 Symbol − MTM GS MIXGAIN MT2 DE2_2 DE2_1 DE2_0 Default 0 0 0 0 1 0 0 0 7 6 5 4 3 2 1 0 Symbol MTNS1 MTNS0 WS_SEL DE_SW MT1 DE1_2 DE1_1 DE1_0 Default 0 0 0 0 0 0 0 0 BIT Table 47 Description of register bits (address 13H) BIT SYMBOL DESCRIPTION 15 - reserved 14 MTM Master mute.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 49 Mixer gain setting MIX(1) MIX_GAIN 1 0 DAC output gain is set to 0 dB and mixer signal output gain is set −6 dB 1 1 DAC output gain and mixer signal output gain are set to 0 dB MIXER OUTPUT GAIN Note 1. See Table 52. Table 50 De-emphasis setting for the incoming signal DE2_2 DE2_1 DE2_0 DE1_2 DE1_1 DE1_0 0 0 0 0 0 1 32 kHz 0 1 0 44.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL UDA1355H DESCRIPTION 7 SILENCE Silence detector overrule. Value to force the DAC output to silence. This will give a plop at the output of the DAC because of mismatch in offsets and the DC offset added to the signal in the interpolator itself.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 54 Data source selector DAC channel 1 and 2; note 1 DAC_CH2_SEL1 DAC_CH2_SEL0 DATA OUTPUT DAC DAC_CH1_SEL1 DAC_CH1_SEL0 0 0 ADC input 0 1 I2S-bus input 1 0 IEC 60958 input 1 1 I2S-bus input Note 1. The change of the data source will take place only when the mix mode is turned on (bit MIX = 1). The channel 2 input selection is valid only when the channel 1 data source is correct.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 58 Description of register bits (address 20H) BIT SYMBOL DESCRIPTION 15 to 8 MA_DECL[7:0] ADC volume setting left channel. Value to program the ADC gain setting for the left channel. The range is from +24 to −63 dB and −∞ dB (see Table 59). 7 to 0 MA_DECR[7:0] ADC volume setting right channel. Value to program the ADC gain setting for the right channel.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 61 Description of register bits (address 21H) BIT 15 SYMBOL DESCRIPTION MT_ADC Mute ADC. If this bit is logic 0 then the ADC is not muted; if this bit is logic 1 then the ADC is muted. 14 to 12 − reserved 11 to 8 PGA_GAIN_CTRLL[3:0] PGA gain control left channel. Value to program the gain of the left input amplifier. There are nine settings (see Table 62).
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT UDA1355H SYMBOL DESCRIPTION − reserved 1 DC_SKIP DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the DC filter is disabled. The DC filter is at the output of the comb filter just before the decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle tones from the audio band).
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 12.2.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 69 Register addresses 51H (left) and 54H (right) BIT 15 14 13 12 11 10 9 8 Symbol SPDO_ BIT39 SPDO_ BIT38 SPDO_ BIT37 SPDO_ BIT36 SPDO_ BIT35 SPDO_ BIT34 SPDO_ BIT33 SPDO_ BIT32 Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol SPDO_ BIT31 SPDO_ BIT30 SPDO_ BIT29 SPDO_ BIT28 SPDO_ BIT27 SPDO_ BIT26 SPDO_ BIT25 SPDO_ BIT24 Default 0 0 0 0 0 0 0 0 BIT Table
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface BIT SYMBOL 29 to 28 SPDO_BIT[29:28] UDA1355H DESCRIPTION Clock accuracy. Value indicating the clock accuracy: 00 = level II 01 = level I 10 = level III 11 = reserved 27 to 24 SPDO_BIT[27:24] Sample frequency. Value indicating the sampling frequency: 0000 = 44.1 kHz 0001 = 48 kHz 0010 = 32 kHz other states = reserved 23 to 20 SPDO_BIT[23:20] Channel number. Value indicating the channel number (see Table 74).
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H SPDO_BIT32 SPDO_BIT35 SPDO_BIT34 SPDO_BIT33 WORD LENGTH 1 0 0 0 indicated 1 0 0 1 20 bits 1 0 1 0 22 bits 1 0 1 1 reserved 1 1 0 0 23 bits 1 1 0 1 24 bits 1 1 1 0 21 bits 1 1 1 1 reserved SPDO_BIT23 SPDO_BIT22 SPDO_BIT21 SPDO_BIT20 0 0 0 0 don’t care 0 0 0 1 A (left for stereo transmission) 0 0 1 0 B (right for stereo transmission) 0 0 1 1 C 0
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H SPDO_BIT19 SPDO_BIT18 SPDO_BIT17 SPDO_BIT16 SOURCE NUMBER 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Table 76 General information SPDO_BIT[15:8] 12.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 78 Description of register bits (address 18H) BIT SYMBOL DESCRIPTION − reserved 6 SDETR2 Silence detector channel 2 right. If this bit is logic 0 then there is no silence detection for the right input of channel 2; if this bit is logic 1 then there is silence detection for the right input of channel 2. 5 SDETL2 Silence detector channel 2 left.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 12.3.3 UDA1355H SPDIF INPUT Table 81 Register address 59H BIT 15 14 13 12 11 10 9 8 Symbol − − − − − − − SPDO_STATUS BIT 7 6 5 4 3 2 1 0 Symbol − − − − − − B_ERR SPDIF_LOCK Table 82 Description of register bits (address 59H) BIT SYMBOL DESCRIPTION − reserved SPDO_STATUS SPDIF encoder output status.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H Table 85 register address 5AH (left) and 5DH (right); see note 1 BIT Symbol BIT Symbol 15 14 13 12 11 10 9 8 SPDI_ BIT15 SPDI_ BIT14 SPDI_ BIT13 SPDI_ BIT12 SPDI_ BIT11 SPDI_ BIT10 SPDI_ BIT9 SPDI_ BIT8 7 6 5 4 3 2 1 0 SPDI_ BIT7 SPDI_ BIT6 SPDI_ BIT5 SPDI_ BIT4 SPDI_ BIT3 SPDI_ BIT2 SPDI_ BIT1 SPDI_ BIT0 Note 1.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 15 CHARACTERISTICS VDD = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA1 DAC supply voltage VDDA2 ADC supply voltage 2.7 3.0 3.6 V VDDX crystal oscillator and PLL supply voltage 2.7 3.0 3.6 V VDDI digital core supply voltage 2.7 3.0 3.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX. UNIT Reference voltage VREF reference voltage on pin REF with respect to VSSA 0.45VDD 0.5VDD 0.55VDD V Digital-to-analog converter Vo(rms) output voltage (RMS value) − 900 − mV ΔVo output voltage unbalance − 0.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX. UNIT IEC 60958 inputs Vi(p-p) input voltage (peak-to-peak value) 0.2 0.5 3.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. TYP. MAX.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface SYMBOL PARAMETER UDA1355H CONDITIONS MIN. 0 TYP. MAX. UNIT − − μs tHD;DAT data hold time tSP pulse width of spikes note 5 0 − 50 ns CL load capacitance for each bus line − − 400 pF Notes 1. In order to prevent digital noise interfering with the L3-bus communication, the rise and fall times should be as small as possible. 2.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 0 L3DATA BIT 7 MGL723 Fig.21 L3-bus interface timing for address mode. handbook, full pagewidth tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA BIT 0 BIT 7 L3DATA read td(L3)R tdis(L3)R MBL566 Fig.
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t BUF t LOW tr tf t HD;STA t SP 70 SCL S t HD;DAT t HIGH t SU;DAT t SU;STA MBC611 P Preliminary specification Fig.23 I2C-bus interface timing.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 17 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 detail X 11 1 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.1 0.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 18 SOLDERING 18.1 UDA1355H If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface 18.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface UDA1355H 19 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1.
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NXP Semiconductors Preliminary specification Stereo audio codec with SPDIF interface Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted.
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NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.