Datasheet

Product data sheet Rev. 1 — 12 February 2015 6 of 25

NXP Semiconductors

TJA1024

Quad LIN 2.2A/SAE J2602 transceiver

7. Functional description

The TJA1024 is the interface between the LIN master/slave protocol controller and the

physical bus in a LIN network. According to the Open System Interconnect (OSI) model,

this interface is the LIN physical layer.

The LIN transceivers are optimized for, but not limited to, automotive applications with

excellent ElectroMagnetic Compatibility (EMC) performance.

7.1 LIN 2.x/SAE J2602 compliant

The TJA1024 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant. The

LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol).

Consequently, nodes containing a LIN 2.2A-compliant physical layer can be combined,

without restriction, with LIN physical layer nodes that comply with earlier revisions

(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1 and LIN 2.2).

7.2 Operating modes

The transceivers are fully operational in Normal mode. A low-power Sleep mode is also

supported, as well as a Reset mode. Standby mode facilitates the transition between

Sleep and Normal modes.

The transceivers operate independently (except in Reset mode; see Section 7.2.4

), so

one transceiver can be in Normal mode while another is in Sleep or Standby etc. Power

consumption is at a minimum when all four transceivers are in Sleep mode.

7.2.1 Normal mode

In Normal mode, the TJA1024 can transmit and receive data via the LIN bus lines. The

transceivers operate independently, so one can be active while the others are off.

A transceiver switches from Sleep or Standby mode to Normal mode if SLPx_N is held

HIGH for t

gotonorm

. If SLPx_N is held LOW for t

gotosleep

, the transceiver switches from

Normal to Sleep mode.

The receivers detect data streams on the LIN bus lines (via pins LINx) and transfer the

input via pins RXDx to the microcontroller (see Figure 6

): HIGH for a recessive level and

LOW for a dominant level on the bus. The receivers have supply-voltage related

thresholds with hysteresis and integrated filters to suppress bus line noise.

Transmit data streams from the protocol controller are detected on the TXDx pins and are

converted by the transmitters into optimized bus signals shaped to minimize EME. The

LIN bus output pins are pulled HIGH via internal slave termination resistors. For a master

application, an external resistor in series with a diode should be connected between pin

BATx

and the appropriate LINx pin (see Figure 6).