Datasheet

TJA1024 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 1 — 12 February 2015 2 of 25
NXP Semiconductors
TJA1024
Quad LIN 2.2A/SAE J2602 transceiver
2.2 Protection
 Very high ElectroMagnetic Immunity (EMI)
 Very high ESD robustness: 8 kV according to IEC 61000-4-2 for pins LINx and V
BATx
 Bus terminal and battery pins protected against transients in the automotive
environment (ISO 7637)
 Bus terminal short-circuit proof to battery and ground
 Thermally protected
 Initial TXD dominant check when switching to Normal mode
 TXD dominant time-out function
3. Quick reference data
4. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
BAT
battery supply voltage pins V
BAT1
and V
BAT2
; limiting values 0.3 - +42 V
operating range 5 - 18 V
I
BAT
battery supply current per pin (V
BAT1
or V
BAT2
):
Sleep mode (both channels); bus recessive
(both channels); V
LINx
=V
BATx
; V
SLPx_N
=0V
2.5 7 10 A
Standby mode (both channels); bus recessive
(both channels); V
LINx
=V
BATx
; V
SLPx_N
=0V
2.5 7 10 A
Normal mode (both channels); bus recessive
(both channels); V
TXDx
=5 V; V
LINx
= V
BATx
;
V
SLPx_N
=5 V
300 1600 3200 A
V
LIN
voltage on pin LIN pins LIN1, LIN2, LIN3 and LIN4; limiting value;
with respect to GND and V
BAT
42 - +42 V
V
ESD
electrostatic discharge voltage on pins LIN1, LIN2, LIN3, LIN4, V
BAT1
and V
BAT2
;
according to IEC 61000-4-2
8- +8kV
T
vj
virtual junction temperature 40 - +150 C
Table 2. Ordering information
Type number Package
Name Description Version
TJA1024HG DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 24 terminals; body 3.5  5.5  0.85 mm
SOT815-1