Datasheet

6
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J2 HEADER – DEFAULT SETTING
J2 Header
Resistor
Default
Setting
Signal
Description
J2-1 R27 open CLK2_SJA Alternative SJA1124 clock reference
J2-2 R26 0 CLK1_SJA SJA1124 clock reference
J2-3 - - - Not connected
J2-4 R21 0 SDI_SJA Shared SJA1124 SPI slave data input
J2-5 R22 0 SDO_SJA Shared SJA1124 SPI slave data output
J2-6 R20 0 SCK_SJA Shared SJA1124 SPI slave clock input
J2-7 - - GND Ground
J2-8 - - - Not connected
J2-9 - - - Not connected
J2-10 - - - Not connected