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S32K1XX

S32K1xx Data Sheet

Caution

• S32K148, S32K142, S32K146, and S32K116 specific

information is preliminary until these devices are

qualified.

Key Features

• Operating characteristics

– Voltage range: 2.7 V to 5.5 V

– Ambient temperature range: -40 °C to 105 °C for

HSRUN, -40 °C to 125 °C for RUN

• ARM™ Cortex-M4F/M0+ core, 32-bit CPU

– Supports up to 112 MHz frequency (HSRUN) with

1.25 Dhrystone MIPS per MHz

– ARM Core based on the ARMv7 Architecture and

Thumb®-2 ISA

– Integrated Digital Signal Processor (DSP)

– Configurable Nested Vectored Interrupt Controller

(NVIC)

– Single Precision Floating Point Unit (FPU)

• Clock interfaces

– 4 - 40 MHz fast external oscillator (SOSC)

– 48 MHz Fast Internal RC oscillator (FIRC)

– 8 MHz Slow Internal RC oscillator (SIRC)

– 128 kHz Low Power Oscillator (LPO)

– Up to 112 MHz (HSRUN) System Phased Lock

Loop (SPLL)

– Up to 50 MHz DC external square wave input clock

– Real Time Counter (RTC)

• Power management

– Low-power ARM Cortex-M4F/M0+ core with

excellent energy efficiency

– Power Management Controller (PMC) with multiple

power modes: HSRUN, Run, Stop, VLPR, and

VLPS

– Supports peripheral specific clock gating. Only

specific peripherals remain working in low power

modes.

• Memory and memory interfaces

– Up to 2 MB program flash memory with ECC

– 64 KB FlexNVM for data flash memory with ECC

and EEPROM emulation

– Up to 256 KB SRAM with ECC

– Up to 4 KB of FlexRAM for use as SRAM or

EEPROM emulation

– Up to 4 KB Code cache to minimize performance

impact of memory access latencies

– QuadSPI with HyperBus™ support

• Mixed-signal analog

– Up to two 12-bit Analog-to-Digital Converter

(ADC) with up to 32 channel analog inputs per

module

– One Analog Comparator (CMP) with internal 8-bit

Digital to Analog Converter (DAC)

• Debug functionality

– Serial Wire JTAG Debug Port (SWJ-DP) combines

– Debug Watchpoint and Trace (DWT)

– Instrumentation Trace Macrocell (ITM)

– Test Port Interface Unit (TPIU)

– Flash Patch and Breakpoint (FPB) Unit

• Human-machine interface (HMI)

– Up to 156 GPIO pins with interrupt functionality

– Non-Maskable Interrupt (NMI)

• Communications interfaces

– Up to three Low Power Universal Asynchronous

Receiver/Transmitter (LPUART) modules with

DMA support and low power availability

– Up to three Low Power Serial Peripheral Interface

(LPSPI) modules with DMA support and low power

availability

– Up to two Low Power Inter-Integrated Circuit

(LPI2C) modules with DMA support and low power

availability

– Up to three FlexCAN modules (with optional CAN-

FD support)

– FlexIO module for flexible and high performance

serial interfaces

NXP Semiconductors

Document Number S32K1XX

Data Sheet: Product Preview

Rev. 4, 06/2017

This document contains information on a product under development. NXP

reserves the right to change or discontinue this product without notice.

Preliminary

Summary of content (70 pages)

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NXP Semiconductors Data Sheet: Product Preview Document Number S32K1XX Rev. 4, 06/2017 S32K1XX S32K1xx Data Sheet Caution • S32K148, S32K142, S32K146, and S32K116 specific information is preliminary until these devices are qualified. Key Features • Operating characteristics – Voltage range: 2.7 V to 5.5 V – Ambient temperature range: -40 °C to 105 °C for HSRUN, -40 °C to 125 °C for RUN • ARM™ Cortex-M4F/M0+ core, 32-bit CPU – Supports up to 112 MHz frequency (HSRUN) with 1.
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• Reliability, safety and security – HW Security Engine (CSEc) – Internal watchdog (WDOG) – External Watchdog monitor (EWM) module – Error-Correcting Code (ECC) on flash and SRAM memories – Cyclic Redundancy Check (CRC) module – 128-bit Unique Identification (ID) number – System Memory Protection Unit (System MPU) • Timing and control – Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM) – One 16-bit Low Power Timer (LPTMR) with flexible wake up control – Two
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Table of Contents 1 Block diagram.................................................................................... 4 2 Feature comparison............................................................................ 5 3 Ordering parts.....................................................................................7 4 6.2.5 6.3 Memory and memory interfaces................................................27 6.3.1 specifications................................................................27 3.
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Block diagram 1 Block diagram Following figures show superset high level architecture block diagrams of S32K14x series and S32K11x series respectively. Other devices within the family have a subset of the features. See Feature comparison for chip specific values.
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Feature comparison IO PORT ARM Cortex M0+ Clock generation IO PORT Serial Wire SW-DP NVIC AHB-AP SIRC 8 MHz LPO 128 kHz AWIC SOSC FIRC 48 MHz 4-40 MHz DMA MUX Unified Bus PPB BPU MTB+DWT eDMA AHBLite AHBLite M2 M0 Crossbar switch (AXBS-Lite) S0 S2 S1 System MPU1 System MPU1 EIM Flash memory controller SRAM2 FlexRAM/ SRAM2 Code flash memory Peripheral bus controller Data flash memory WDOG ERM LPI2C 12-bit ADC FlexIO Low Power Timer LPIT CSEc CMP 8-bit DAC CMU CRC LPUA
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Feature comparison S32K14x S32K11x K116 Parameter K118 K142 K146 K144 ARM® Cortex™-M0+ Core 48 MHz Frequency K148 ARM® Cortex™-M4F up to 112 MHz (HSRUN) IEEE-754 FPU HW security module (CSEc)1 1x 1x capable up to ASIL-B capable up to ASIL-B up to 48 MHz up to 112 MHz (HSRUN) 1x 1x CRC module ISO 26262 Peripheral speed System Crossbar DMA EWM Memory protection unit FIRC CMU Watchdog Low power modes HSRUN mode up to 58 up to 43 Number of I/Os up to 89 up to 128 2.7 - 5.
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Ordering parts 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search. Additionally see the attachment S32K_Part_Numbers.xlsx . NOTE Not all part number combinations exist S32K1xx Data Sheet, Rev.
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Ordering parts 3.2 Ordering information F/P S32 K 1 0 0 X Y F0 M LC R Product status Product type/brand Product line Series/Family (including generation) Core platform/ Performance Memory size Ordering option 1: Letter Ordering option 2: Letter Fab and Mask rev.
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General 4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device.
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General TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode • Assumes maximum θJA for 2s2p board. See Thermal characteristics 8. 60 seconds lifetime; device in reset (no outputs enabled/toggling) 4.2 Voltage and current operating requirements NOTE Full functionality/specifications cannot be guaranteed when voltage drops below 2.7 V. Table 2. Voltage and current operating requirements 1 Symbol 2 VDD VDD_OFF VDDA VDD – VDDA Description Min. Max. Unit Notes Supply voltage 2.73 5.
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General 4.3 Thermal operating characteristics Table 3. Thermal operating characteristics for 64 LQFP, 100 LQFP, and 100 MAP-BGA packages. Symbol TA C-Grade Part TJ C-Grade Part TA V-Grade Part TJ V-Grade Part TA M-Grade Part TJ M-Grade Part Parameter Value Ambient temperature under bias Junction temperature under bias Ambient temperature under bias Junction temperature under bias Ambient temperature under bias Junction temperature under bias Unit Min. Typ. Max.
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General 4.
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General VREFH VREFL VSSA VDD VDDA • No trace exceeding 1 mm from the protection to the trace or to the ground. • The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm). • The ground of the protection is connected as short as possible to the ground plane under the integrated circuit. VOSC = 3.3 V nominal FIRC SIRC SPLL SOSC ADC CMP VCORE = 1.2 V/1.4 V nominal VFlash = 3.
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General Table 5. VDD supply LVR, LVD and POR operating requirements (continued) Symbol VLVD VLVD_HYST VLVW VLVW_HYST VBG Description Min. Typ. Max. Unit Falling low-voltage detect threshold 2.8 2.875 3 V LVD hysteresis — 50 — mV 4.19 4.305 4.5 V — 75 — mV 0.97 1.00 1.03 V Falling low-voltage warning threshold LVW hysteresis Bandgap voltage reference Notes 1 1 1. Rising threshold is the sum of falling threshold and hysteresis voltage. 4.
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General Table 6. Power mode transition operating behaviors (continued) Symbol Description Min. Typ. Max. Unit VLPS → RUN 8 — 17 μs STOP1 → RUN 0.07 0.075 0.08 μs STOP2 → RUN 0.07 0.075 0.08 μs VLPR → RUN 19 — 26 μs VLPR → VLPS 5.75 6.25 6.5 μs VLPS → VLPR 26.5 27.25 27.75 μs RUN → Compute operation 0.35 0.38 0.4 μs HSRUN → Compute operation 0.3 0.31 0.35 μs RUN → STOP1 0.35 0.38 0.4 μs RUN → STOP2 0.2 0.23 0.25 μs RUN → VLPS 0.35 0.38 0.
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S32K142 NXP Semiconductors S32K144 Idd/MH z (μA/ MHz)5 Peripherals enabled HSRUN@112 MHz (mA) 4 Peripherals disabled Peripherals enabled TBD RUN@80 MHz (mA) Peripherals disabled TBD Peripherals enabled 12 Peripherals disabled 7 RUN@64 MHz (mA) 25 Typ 26 38 105 Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD TBD TBD TBD TBD TBD TBD TBD 125 Max TBD TBD TBD TBD TBD TBD TBD 40 TBD 25 Typ 26 38 7 12 TBD TBD 105 Typ TBD TBD TBD TBD TBD TBD TBD T
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Ambient Temperature (°C) NXP Semiconductors Table 7. Power consumption (Typicals unless stated otherwise) 1 (continued) 85 S32K1xx Data Sheet, Rev. 4, 06/2017 Preliminary S32K1487, 8 RUN@48 MHz (mA) RUN@64 MHz (mA) RUN@80 MHz (mA) HSRUN@112 MHz (mA) 4 Idd/MH z (μA/ MHz)5 159 1.72 1.85 7.2 8.1 20.4 27.1 26.1 33.5 30.5 40 43.9 56.1 381 Max 359 384 2.60 2.65 8.3 9.2 21.9 28.5 27.8 34.4 32.9 41.5 45.5 57.5 411 Typ 256 273 1.80 2.10 7.8 8.5 20.6 27.4 26.6 33.
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I/O parameters 4.7.1 Modes configuration Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes used in gathering the power consumption data stated in the above table Table 7. For full functionality refer to table: Module operation in available low power modes of the Reference Manual. 4.8 ESD handling ratings Symbol Description VHBM Electrostatic discharge voltage, human body model VCDM Electrostatic discharge voltage, charged-device model ILAT Min. Max.
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I/O parameters Figure 7. Input signal measurement reference 5.2 General AC specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 8. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
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I/O parameters Table 9. DC electrical specifications at 3.3 V Range (continued) Symbol Parameter Value Unit Notes Min. Typ. Max. I/O current sink capability measured when pad = 0.8 V 3 — — mA Ioh_Strong I/O current source capability measured when pad = (VDDE − 0.8 V) 14 — — mA 4 Iol_Strong I/O current sink capability measured when pad = 0.
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I/O parameters Table 10. DC electrical specifications at 5.0 V Range (continued) Symbol Parameter Value Min. Typ. Max. Unit Notes Ioh_Strong I/O current source capability measured when pad = VDDE - 0.8 V 20 — — mA 3, 4 Iol_Strong I/O current sink capability measured when pad = 0.8 V 20 — — mA 4, 5 IOHT Output high current total for all ports — — 100 mA IIN Input leakage current (per pin) for full temperature range at VDD = 5.5 V 6 All pins other than high drive port pins 0.
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I/O parameters 5.6 AC electrical specifications at 5 V range Table 12. AC electrical specifications at 5 V Range Symbol Standard Strong DSE NA 0 1 Rise time (nS)1 Fall time (nS) 1 Min. Max . Min. Max. 3.2 9.4 3.6 10.7 Capacitance (pF) 2 25 5.4 15.7 5.1 17.4 50 18.5 52.6 17.6 59.7 200 4.0 9.4 3.6 10.7 25 5.8 15.7 5.1 17.4 50 18.1 52.6 17.6 59.7 200 1.6 4.6 1.5 5.0 25 2.2 5.7 2.2 5.8 50 5.6 14.6 5.0 15.4 200 1. For reference only.
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Peripheral operating requirements and behaviors Table 14. Device clock specifications 1 (continued) Symbol Description Max. Unit fSYS System and core clock — 48 MHz fBUS Bus clock — 24 MHz — 24 MHz fFLASH Flash clock Normal run mode (S32K14x series) 3 fSYS System and core clock — 80 MHz fBUS Bus clock — 40 MHz — 26.67 MHz fFLASH Flash clock VLPR 1. 2. 3. 4. Min.
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Clock interface modules Single input comparator (EXTAL WAVE) ref_clk Mux Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 280 ohms ESD PAD 40 ohms XTAL pin EXTAL pin Series resistor for current limitation 1M ohms Feedback Resistor Crystal or resonator C1 C2 Figure 8. Oscillator connections scheme Table 15. External System Oscillator electrical specifications Symbol Description Min. Typ. Max.
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Clock interface modules Table 15. External System Oscillator electrical specifications (continued) Symbol Description Min. Typ. Max. Unit — 1 — MΩ Low-gain mode (HGO=0) — 0 — kΩ High-gain mode (HGO=1) — 0 — kΩ High-gain mode (HGO=1) RS Notes Series resistor Vpp Peak-to-peak amplitude of oscillation (oscillator mode) 3 Low-gain mode (HGO=0) — 1.0 — V High-gain mode (HGO=1) — 3.3 — V 1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit.
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System Clock Generation (SCG) specifications 6.2.3 System Clock Generation (SCG) specifications 6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications Table 17. Fast internal RC Oscillator electrical specifications Parameter1 Symbol Value Unit Min. Typ. Max. FIRC target frequency — 48 — MHz ΔF Frequency deviation across process, voltage, and temperature < 105°C — ±0.5 ±1 %FFIRC ΔF125 Frequency deviation across process, voltage, and temperature < 125°C — ±0.5 ±1.
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Memory and memory interfaces 6.2.4 Low Power Oscillator (LPO) electrical specifications Table 19. Low Power Oscillator (LPO) electrical specifications Symbol Parameter FLPO Internal low power oscillator frequency Tstartup Startup Time Min. Typ. Max. Unit 113 128 139 kHz — — 20 µs 6.2.5 SPLL electrical specifications Table 20. SPLL electrical specifications Symbol Parameter 1 2 FSPLL_REF FSPLL_Input Min. Typ. Max.
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Memory and memory interfaces 6.3.1.1 Flash timing specifications — commands Table 21. Flash command timing specifications Symbol Description1 trd1blk64k Read 1s Block execution time • 64 KB data flash trd1blk512k • 512 KB program flash Min. Typ. Max. Unit — — 0.5 ms — — 1.
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Memory and memory interfaces Table 21. Flash command timing specifications (continued) Symbol teewr16b64k Description1 • 48 KB EEPROM backup Min. Typ. Max.
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Memory and memory interfaces Table 22. NVM reliability specifications (continued) Symbol Description Min. Typ. Max. Unit tnvmretp1k Data retention after up to 1 K cycles 20 — — years nnvmcycp Cycling endurance 1K — — cycles Notes 2, 1 When using FlexMemory feature: FlexRAM as Emulated EEPROM tnvmretee nnvmwree16 nnvmwree256 Data retention Write endurance • EEPROM backup to FlexRAM ratio = 16 • EEPROM backup to FlexRAM ratio = 256 5 — — years 100 K — — writes 1.
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NXP Semiconductors Table 23.
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FLASH PORT Sym Unit FLASH A RUN1 HSRUN1 SDR SDR QuadSPI Mode Internal Sampling N1 Min Max FLASH B Internal DQS Internal Sampling PAD Loopback Internal Loopback Min Min Max Max Internal DQS N1 Min Max RUN/HSRUN2 PAD Loopback Internal Loopback Min Min Max Max SDR DDR3 Internal Sampling External DQS N1 Extrenal DQS Min Max Min Max 2.5 - 10 - 14 - 1.
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Memory and memory interfaces 1 2 Clock 3 tSCK tSDC tSDC SCK CS tIH tIS Data in Figure 9. QuadSPI input timing (SDR mode) diagram 1 2 3 Clock tSCK tSDC tSDC SCK tSCKCS tCSSCK CS tIV tOV Data out Figure 10. QuadSPI output timing (SDR mode) diagram tSCK RWDS tSDC tSDC tIS tIH DI[7:0] Figure 11. QuadSPI input timing (HyperRAM mode) diagram S32K1xx Data Sheet, Rev.
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Analog modules CK tIV tOV Output Invalid Data Figure 12. QuadSPI output timing (HyperRAM mode) diagram 6.4 Analog modules 6.4.1 ADC electrical specifications 6.4.1.1 12-bit ADC operating conditions Table 24. 12-bit ADC operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -0.1 0 +0.
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ADC electrical specifications Table 24. 12-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes CP2 Analog Bus Capacitance — — 4 pF CS Sampling capacitance — 4 5 pF fADCK ADC conversion clock frequency Normal usage 2 40 50 MHz 4, 5 fCONV ADC conversion frequency No ADC hardware averaging.6 Continuous conversions enabled, subsequent conversion time 46.4 928 1160 Ksps 7, 8 ADC hardware averaging set to 32.
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ADC electrical specifications 6.4.1.2 12-bit ADC electrical characteristics NOTE ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions. Table 25.
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ADC electrical specifications Table 26. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS) (continued) Symbol Description Conditions 1 Min. Typ.2 Max. Unit Notes TUE4 Total unadjusted error — ±4 ±8 LSB5 6, 7, 8, 9 DNL Differential non-linearity — ±0.7 — LSB5 6, 7, 8, 9 INL Integral non-linearity — ±1.0 — LSB5 6, 7, 8, 9 1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to half the ADC clock frequency.
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ADC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications (continued) Symbol Description VAIN Analog input voltage VAIO Analog input offset voltage, High-speed mode -40 - 125 ℃ VAIO Typ. Max. Unit 0 0 - VDDA VDDA V mV -25 mV -40 Propagation delay, High-speed — Propagation delay, High-speed 300 Propagation delay, Low-speed — 0.5 2 — 0.
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ADC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications (continued) Symbol IDAC8b 1. 2. 3. 4. 5. 6. Description Min. Typ. Max. Unit 3.3V Reference Voltage — 6 9 μA 5V Reference Voltage — 10 16 μA 8-bit DAC current adder (enabled) INL5 8-bit DAC integral non-linearity –0.75 — 0.75 LSB6 DNL 8-bit DAC differential non-linearity –0.5 — 0.
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ADC electrical specifications Figure 15. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1) Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0) S32K1xx Data Sheet, Rev.
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Communication modules Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1) 6.5 Communication modules 6.5.1 LPUART electrical specifications Refer to General AC specifications for LPUART specifications. 6.5.1.1 Supported baud rate Baud rate = Baud clock / ((OSR+1) * SBR). For details, see section: 'Baud rate generation' of the Reference Manual. 6.5.
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Num Symbol Description Run Mode2 Conditions 5.0 V IO HSRUN Mode2 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
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NXP Semiconductors Table 29. LPSPI electrical specifications1 (continued) Num Symbol Description Run Mode2 Conditions 5.0 V IO Min. Master HSRUN Mode2 3.3 V IO Max. Min. - Max. 5.0 V IO Min. - Max. VLPR Mode 3.3 V IO Min. - Max. 5.0 V IO Min. - Max. Unit 3.3 V IO Min. - Max.
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Symbol Description Run Mode2 Conditions 5.0 V IO Min. Preliminary Min. Max. Min. Max. 5.0 V IO Min. Max. 3.3 V IO Min. Max. ns tSPSCK/2 + 5 tSPSCK/2 - 5 tSPSCK/2 + 5 tSPSCK/2 - 5 tSPSCK/2 + 3 tSPSCK/2 - 3 tSPSCK/2 + 3 tSPSCK/2 + 3 Master Loopback5 tSPSCK/2 - 3 S32K1xx Data Sheet, Rev. 4, 06/2017 Data setup time(inputs) Max. 3.3 V IO Unit Master 6 tSU Min. 5.0 V IO VLPR Mode Slave Master Loopback(slow) 6 3.3 V IO Max.
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NXP Semiconductors Table 29. LPSPI electrical specifications1 (continued) Num Symbol Description Run Mode2 Conditions 5.0 V IO 10 tv Data valid (after SPSCK edge) HSRUN Mode2 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
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6. 7. 8. tperiph = 1/fperiph Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pad used is PTB2. Applicable only for LPSPI0.
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Communication modules SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 12 13 12 13 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 10 MOSI (OUTPUT) MSB OUT2 11 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. LPSPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 5 13 12 13 4 7 MSB IN2 BIT 6 . . .
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Communication modules SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) see note SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN BIT 6 . . . 1 LSB IN Figure 20. LPSPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note 8 MOSI (INPUT) SLAVE 13 12 13 11 10 MISO (OUTPUT) 12 MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . .
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Communication modules 6.5.4 FlexCAN electical specifications For supported baud rate, see section 'Protocol timing' of the Reference Manual. 6.5.5 SAI electrical specifications The following table describes the SAI electrical characteristics. • Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). • I/O operating voltage ranges from 2.97 V to 3.
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Communication modules S1 S2 S2 SAI_MCLK (output) S3 SAI_BCLK (output) S4 S4 S12 S11 SAI_FS (output) S10 S9 SAI_FS (input) S7 S8 S7 S8 SAI_TXD S5 S6 SAI_RXD Figure 22. SAI Timing — Master modes Table 31. Slave mode timing specifications Symbol — Description Operating voltage Min. Max. Unit 2.97 3.
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Communication modules S13 S14 SAI_BCLK (input) S14 S21 S22 SAI_FS (output) S19 S20 SAI_FS (input) S17 S18 S17 S18 SAI_TXD S15 S16 SAI_RXD Figure 23. SAI Timing — Slave modes 6.5.6 Ethernet AC specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. The following table describes the MII electrical characteristics.
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Communication modules MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 24. MII receive diagram MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 25. MII transmit signal diagram The following table describes the RMII electrical characteristics. • Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
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Communication modules Table 33. RMII signal switching specifications (continued) Symbol Description Min. Max. Unit RMII7 RMII_CLK to TXD[1:0], TXEN invalid 2 — ns RMII8 RMII_CLK to TXD[1:0], TXEN valid — 15 ns RMII2 RMII1 RMII3 RMII4 RMII_CLK(input) RXD[n:0] Valid data CRS_DV Valid data RXER Valid data Figure 26. RMII receive diagram RMII6 RMII5 RMII_CLK (input) RMII8 RMII7 TXD[n:0] Valid data TXEN Valid data Figure 27.
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Debug modules Table 34. MDIO timing specifications (continued) Symbol Description Min. Max.
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Symbol Description Run Mode 5.0 V IO HSRUN Mode 3.3 V IO 5.0 V IO VLPR Mode 3.3 V IO 5.0 V IO Unit 3.3 V IO Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. S32K1xx Data Sheet, Rev.
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Debug modules S2 S3 S3 SWD_CLK (input) S4 S4 Figure 29. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 S13 SWD_DIO Output data valid S12 SWD_DIO Figure 30. Serial wire data timing 6.6.2 Trace electrical specifications The following table describes the Trace electrical characteristics. • Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1).
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Debug modules Table 36. Trace specifications (continued) Symbol Trace on fast pads fTRACE RUN Mode Max Trace frequency 80 HSRUN Mode VLPR Mode Unit 48 40 74.667 80 4 MHz tDVO Data Output Valid 4 4 4 4 4 20 ns tDIV Data Output Invalid -2 -2 -2 -2 -2 -10 ns 24 20 22.4 22.86 4 MHz fTRACE Trace on slow pads Description Max Trace frequency 22.86 tDVO Data Output Valid 8 8 8 8 8 20 ns tDIV Data Output Invalid -4 -4 -4 -4 -4 -10 ns Figure 31.
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Symbol Description Run Mode 5.0 V IO Min. 3.3 V IO Max. Min. 5.0 V IO Max. Min. VLPR Mode 3.3 V IO Max. Min. 5.0 V IO Max. Min. Unit 3.3 V IO Max. Min. Max. TCLK frequency of operation MHz Boundary Scan - 20 - 20 - 20 - 20 - 10 - 10 JTAG - 20 - 20 - 20 - 20 - 10 - 10 - 1/JI - 1/JI - 1/JI - 1/JI - 1/JI - Preliminary J2/2 + 5 J2/2 - 5 J2/2 + 5 J2/2 - 5 J2/2 + 5 J2/2 - 5 S32K1xx Data Sheet, Rev.
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Debug modules J2 J3 J3 TCLK (input) J4 J4 Figure 32. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 J8 Data outputs Output data valid J9 Data outputs Figure 33. Boundary scan (JTAG) timing S32K1xx Data Sheet, Rev.
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Thermal attributes TCLK J10 TDI/TMS J11 Input data valid J12 J13 TDO Output data valid J14 TDO Figure 34. Test Access Port timing 7 Thermal attributes 7.1 Description The tables in the following sections describe the thermal characteristics of the device.
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NXP Semiconductors Table 38. Thermal characteristics for the 64/100/144/176-pin LQFP package Rating Conditions Symbol Packages Values S32K11x S32K142 S32K144 Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Thermal resistance, Junction to Ambient (Natural Convection)1 Preliminary S32K1xx Data Sheet, Rev.
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Rating Conditions Symbol Packages Values S32K11x S32K142 S32K144 Thermal resistance, Junction to Case 5 Thermal resistance, Junction to Package Top6 Preliminary S32K1xx Data Sheet, Rev. 4, 06/2017 1. 2. 3. 4. 5. 6.
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NXP Semiconductors Table 39. Thermal characteristics for the 100 MAPBGA package Rating Conditions Symbol Values Unit S32K146 S32K144 S32K148 Thermal resistance, Junction to Ambient (Natural Convection) 1, 2 Single layer board (1s) RθJA 57.2 61.0 52.5 °C/W Thermal resistance, Junction to Ambient (Natural Convection) 1, 2, 3 Four layer board (2s2p) RθJA 32.1 35.6 27.5 °C/W RθJMA 44.1 46.6 39.0 °C/W RθJMA 27.2 30.9 22.
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Thermal attributes 7.3 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from this equation: where: • TA = ambient temperature for the package (°C) • RθJA = junction to ambient thermal resistance (°C/W) • PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance.
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Dimensions To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: where: • TT = thermocouple temperature on top of the package (°C) • ΨJT = thermal characterization parameter (°C/W) • PD = power dissipation in the package (W) The thermal characterization parameter is meas
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Pinouts 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. 10 Revision History The following table provides a revision history for this document. Table 40. Revision History Rev. No.
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Revision History Table 40. Revision History Rev. No. Date Substantial Changes • • • • • • • • • • • • • • • Added footnotes Vih Input Buffer High Voltage and Vih Input Buffer Low Voltage Updated table: AC electrical specifications at 3.
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Revision History Table 40. Revision History (continued) Rev. No. Date Substantial Changes • • • • • • • • • • • 3 14 March 2017 4 02 June 2017 • Updated values for VREFH and VREFL to add refernce to the section "voltage and current operating requirments" for Min and Max valaues • Updated footnote to Typ. • Removed footnote from RAS Analog source resistance • Updated figure: ADC input impedance equivalency diagram In table: 12-bit ADC characteristics (2.
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Revision History Table 40. Revision History Rev. No. Date Substantial Changes • • • • • • • • • • • • • • • • • • Updated note 'All the limits defined ... ' • Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS. In Table 2, • Updated parameter IINJPAD_DC_OP and IINJSUM_DC_OP.
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