Datasheet

Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
Table 40. Revision History
Rev. No. Date Substantial Changes
1 12 Aug 2016 Initial release
2 03 March 2017 • Updated descpition of QSPI and Clock interfaces in Key Features section
• Updated figure: High-level architecture diagram for the S32K1xx family
• Updated figure: S32K1xx product series comparison
• Added note in section Determining valid orderable parts
• Updated figure: Ordering information
• In table: Absolute maximum ratings :
• Added footnote to I
INJPAD_DC
• Updated min and max value of I
INJPAD_DC
• Updated description, max and min values for I
INJSUM
• Updated V
IN_TRANSIENT
• In table: Voltage and current operating requirements :
• Renamed V
SUP_OFF
• Updated max value of V
DD_OFF
• Removed V
INA
and V
IN
• Added V
REFH
and V
REFL
• Updated footnote "Typical conditions assumes V
DD
= V
DDA
= V
REFH
= 5
V ...
• Removed I
NJSUM_AF
• Updated footnotes in table Table 4
• Updated section Power mode transition operating behaviors
• In table: Power consumption
• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "
• Updated conditions for VLPR
• Removed Idd/MHz for S32K144
• Updated numbers for S32K142 and S32K148
• Removed use case footnotes
• In section Modes configuration :
• Replaced table "Modes configuration" with spreadsheet attachment:
'S32K1xx_Power_Modes _Master_configuration_sheet'
• In table: DC electrical specifications at 3.3 V Range :
• Added footnotes to V
ih
Input Buffer High Voltage and V
ih
Input Buffer
Low Voltage
• Added footnote to High drive port pins
• In table: DC electrical specifications at 5.0 V Range :
Table continues on the next page...
9
Pinouts
S32K1xx Data Sheet, Rev. 4, 06/2017
66
Preliminary
NXP Semiconductors