Datasheet

Table 37. JTAG electrical specifications
Symbol Description Run Mode HSRUN Mode VLPR Mode Unit
5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
JI TCLK frequency of operation MHz
Boundary Scan - 20 - 20 - 20 - 20 - 10 - 10
JTAG - 20 - 20 - 20 - 20 - 10 - 10
J2 TCLK cycle period 1/JI - 1/JI - 1/JI - 1/JI - 1/JI - 1/JI - ns
J3 TCLK clock pulse width ns
Boundary Scan
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
JTAG
J4 TCLK rise and fall times - 1 - 1 - 1 - 1 - 1 - 1 ns
J5 Boundary scan input data
setup time to TCLK rise
5 - 5 - 5 - 5 - 15 - 15 - ns
J6 Boundary scan input data
hold time after TCLK rise
5 - 5 - 5 - 5 - 8 - 8 - ns
J7 TCLK low to boundary scan
output data valid
- 28 - 32 - 28 - 32 - 80 - 80 ns
J8 TCLK low to boundary scan
output data invalid
0 - 0 - 0 - 0 - 0 - 0 -
J9 TCLK low to boundary scan
output high-Z
- 28 - 32 - 28 - 32 - 80 - 80 ns
J10 TMS, TDI input data setup
time to TCLK rise
3 - 3 - 3 - 3 - 15 - 15 - ns
J11 TMS, TDI input data hold
time after TCLK rise
2 - 2 - 2 - 2 - 8 - 8 - ns
J12 TCLK low to TDO data valid - 28 - 32 - 28 - 32 - 80 - 80 ns
J13 TCLK low to TDO data
invalid
0 - 0 - 0 - 0 - 0 - 0 - ns
J14 TCLK low to TDO high-Z - 28 - 32 - 28 - 32 - 80 - 80 ns
Debug modules
S32K1xx Data Sheet, Rev. 4, 06/2017
58
Preliminary
NXP Semiconductors