Datasheet

Table 35. SWD electrical specifications
Symbol Description Run Mode HSRUN Mode VLPR Mode Unit
5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
S1 SWD_CLK frequency of
operation
- 25 - 25 - 25 - 25 - 10 - 10 MHz
S2 SWD_CLK cycle period 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - 1/S1 - ns
S3 SWD_CLK clock pulse width
S2/2 - 5
S2/2 + 5
S2/2 - 5
S2/2 + 5
S2/2 - 5
S2/2 + 5
S2/2 - 5
S2/2 + 5
S2/2 - 5
S2/2 + 5
S2/2 - 5
S2/2 + 5
ns
S4 SWD_CLK rise and fall times - 1 - 1 - 1 - 1 - 1 - 1 ns
S9 SWD_DIO input data setup time
to SWD_CLK rise
4 - 4 - 4 - 4 - 16 - 16 - ns
S10 SWD_DIO input data hold time
after SWD_CLK rise
3 - 3 - 3 - 3 - 10 - 10 - ns
S11 SWD_CLK high to SWD_DIO
data valid
- 28 - 38 - 28 - 38 - 70 - 77 ns
S12 SWD_CLK high to SWD_DIO
high-Z
- 28 - 38 - 28 - 38 - 70 - 77 ns
S13 SWD_CLK high to SWD_DIO
data invalid
0 - 0 - 0 - 0 - 0 - 0 - ns
Debug modules
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
55