Datasheet

Table 34. MDIO timing specifications (continued)
Symbol Description Min. Max. Unit
MDC1 MDC pulse width high 40% 60% MDC period
MDC2 MDC pulse width low 40% 60% MDC period
MDC3 MDIO (input) to MDC rising edge setup 25 — ns
MDC4 MDIO (input) to MDC rising edge hold 0 — ns
MDC5 MDC falling edge to MDIO output valid
(maximum propagation delay)
— 25 ns
MDC6 MDC falling edge to MDIO output invalid
(minimum propagation delay)
-10 — ns
MDC (output)
MDIO (output)
MDIO (input)
MDC6
MDC5
MDC3
MDC4
MDC1
MDC2
Figure 28. MII/RMII serial management channel timing diagram
6.5.7
Clockout frequency
Maximum supported clock out frequency for this device is 20 MHz
Debug modules
6.6.1
SWD electrical specofications
6.6
Debug modules
S32K1xx Data Sheet, Rev. 4, 06/2017
54
Preliminary
NXP Semiconductors