Datasheet

S1 S2 S2
S3
S4
S4
S11
S9
S7
S5 S6
S7
S8
S12
S10
S8
SAI_MCLK (output)
SAI_BCLK (output)
SAI_FS (output)
SAI_FS (input)
SAI_TXD
SAI_RXD
Figure 22. SAI Timing — Master modes
Table 31. Slave mode timing specifications
Symbol Description Min. Max. Unit
— Operating voltage 2.97 3.6 V
S13 SAI_BCLK cycle time (input) 80 — ns
S14
1
SAI_BCLK pulse width high/low
(input)
45% 55% BCLK period
S15 SAI_RXD input setup before
SAI_BCLK
8 — ns
S16 SAI_RXD input hold after
SAI_BCLK
2 — ns
S17 SAI_BCLK to SAI_TXD output
valid
— 28 ns
S18 SAI_BCLK to SAI_TXD output
invalid
0 — ns
S19 SAI_FS input setup before
SAI_BCLK
8 — ns
S20 SAI_FS input hold after SAI_BCLK 2 — ns
S21 SAI_BCLK to SAI_FS output valid — 28 ns
S22 SAI_BCLK to SAI_FS output
invalid
0 — ns
1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle
input must be taken care during the board design or by the master timing.
Communication modules
S32K1xx Data Sheet, Rev. 4, 06/2017
50
Preliminary
NXP Semiconductors