Datasheet

Crossbar switch (AXBS-Lite)
eDMA
DMA
MUX
SW-DP
Unified Bus
Serial Wire
AHBLite
AHBLite
AWIC
S0
S1
Clock
LPO
128 kHz
generation
FIRC
48 MHz
SOSC
4-40 MHz
SIRC
8 MHz
Peripheral bus controller
CRC
WDOG
LPIT
LPI2C
FlexIO
Low Power
Timer
12-bit ADC
TRGMUX
LPUART
LPSPI
FlexCAN
FlexTimer
PDB
LPIT
RTC
CMP
8-bit DAC
ERM
CMU
GPIO
M0
M2
Flash memory
controller
Data flash
memory
FlexRAM/
SRAM
2
Code flash
memory
EIM
SRAM
2
IO PORT
NVIC
PPB
MTB+DWT
BPU
AHB-AP
ARM Cortex M0+
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
Key:
Device architectural IP
on all S32K devices
(see the "Feature Comparison"
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The ARM M0+ core version in this family
does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
section in the RM)
S2
IO PORT
CSEc
System MPU
1
System MPU
1
Figure 2. High-level architecture diagram for the S32K11x family
2
Feature comparison
The following figure summarizes the memory and package options for the S32K product
series and demonstrates where this device fits within the overall series. All devices which
share a common package are pin-to-pin compatible.
Feature comparison
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
5