Datasheet

Table 29. LPSPI electrical specifications1 (continued)
Num Symbol Description Conditions Run Mode
2
HSRUN Mode
2
VLPR Mode Unit
5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO 5.0 V IO 3.3 V IO
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
10 t
v
Data valid
(after
SPSCK
edge)
Slave - 30 - 39 - 26 - 36 - 92 - 96 ns
Master - 12 - 16 - 11 - 15 - 47 - 48
Master
Loopback
5
- 12 - 16 - 11 - 15 - 47 - 48
Master
Loopback(slow)
6
- 8 - 10 - 7 - 9 - 44 - 44
11 t
HO
Data hold
time(outputs)
Slave 4 - 4 - 4 - 4 - 4 - 4 - ns
Master -15 - -22 - -15 - -23 - -22 - -29 -
Master
Loopback
5
-10 - -14 - -10 - -14 - -14 - -19 -
Master
Loopback(slow)
6
-15 - -22 - -15 - -22 - -21 - -27 -
12 t
RI/FI
Rise/Fall
time input
Slave - 1 - 1 - 1 - 1 - 1 - 1 ns
Master - - - - - -
Master
Loopback
5
- - - - - -
Master
Loopback(slow)
6
- - - - - -
13 t
RO/FO
Rise/Fall
time output
Slave - 25 - 25 - 25 - 25 - 25 - 25 ns
Master - - - - - -
Master
Loopback
5
- - - - - -
Master
Loopback(slow)
6
- - - - - -
1. Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
2. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
3. f
periph
= LPSPI peripheral clock
Communication modules
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
45