Datasheet

1 Block diagram
Following figures show superset high level architecture block diagrams of S32K14x
series and S32K11x series respectively. Other devices within the family have a subset of
the features. See Feature comparison for chip specific values.
Mux
Trace
port
Crossbar switch (AXBS-Lite)
eDMA
DMA
MUX
Core
Peripheral bus controller
CRC
WDOG
S1
M0
M1
DSP
NVIC
ITM
FPB
DWT
AWIC
SWJ-DP
TPIU
JTAG &
Serial Wire
ARM Cortex M4F
ICODE
DCODE
AHB-AP
PPB
System
M2
S2
GPIO
Mux
FPU
Clock
SPLL
LPO
128 kHz
Async
512B
TCD
LPIT
LPI2C
FlexIO
Flash memory
controller
Code flash
S0
Data flash
Low Power
Timer
12-bit ADC
TRGMUX
LPUART
LPSPI
FlexCAN
FlexTimer
PDB
generation
LPIT
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
Key:
Device architectural IP
on all S32K devices
S3
FIRC
48 MHz
M3
ENET
SAI
SOSC
8-40 MHz
(see the "Feature Comparison"
memory
memory
4-40 MHz
QuadSPI
RTC
CMP
8-bit DAC
SIRC
8 MHz
FlexRAM/
SRAM
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The ARM M4 core version in this family
does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K14x Series Reference Manual.
section in the RM)
ERM
EWM
MCM
Lower region
Upper region
Main SRAM
2
Code Cache
System MPU
1
EIM
LMEM
controller
LMEM
QSPI
CSEc
System MPU
1
System MPU
1
System MPU
1
Figure 1. High-level architecture diagram for the S32K14x family
Block diagram
S32K1xx Data Sheet, Rev. 4, 06/2017
4
Preliminary
NXP Semiconductors