Datasheet

Table 24. 12-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.
1
Max. Unit Notes
C
P2
Analog Bus Capacitance — — 4 pF
C
S
Sampling capacitance — 4 5 pF
f
ADCK
ADC conversion clock
frequency
Normal usage 2 40 50 MHz 4, 5
f
CONV
ADC conversion frequency No ADC hardware
averaging.
6
Continuous
conversions enabled,
subsequent conversion
time
46.4 928 1160 Ksps 7, 8
ADC hardware averaging
set to 32.
6
Continuous
conversions enabled,
subsequent conversion
time
1.45 29 36.25 Ksps 7, 8
1. Typical values assume V
DDA
= 5 V, Temp = 25 °C, f
ADCK
= 40 MHz, R
AS
=20 Ω, and C
AS
=10 nF unless otherwise stated.
Typical values are for reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated V
REFH
and V
REFL
pins, V
REFH
is internally tied to V
DDA
, and V
REFL
is internally tied to V
SS
.
To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for
details.
4. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .
5. ADC conversion will become less reliable above maximum frequency.
6. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.
7. Numbers based on the minimum sampling time of 275 ns.
8. For guidelines and examples of conversion rate calculation, see the Reference Manual or download the ADC calculator
tool.
Figure 13. ADC input impedance equivalency diagram
ADC electrical specifications
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
35