Datasheet

1 2 3
t
SCK
t
IS
t
IH
Clock
SCK
CS
Data in
t
SDC
t
SDC
Figure 9. QuadSPI input timing (SDR mode) diagram
1 2 3
t
IV
t
OV
t
SCK
t
CSSCK
t
SCKCS
Clock
SCK
CS
Data out
t
SDC
t
SDC
t
SDC
Figure 10. QuadSPI output timing (SDR mode) diagram
t
IS
RWDS
DI[7:0]
t
IH
t
SCK
t
SDC
t
SDC
Figure 11. QuadSPI input timing (HyperRAM mode) diagram
Memory and memory interfaces
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
33