Datasheet

Table 23. QuadSPI electrical specifications (continued)
FLASH PORT Sym Unit FLASH A FLASH B
RUN
1
HSRUN
1
RUN/HSRUN
2
QuadSPI Mode SDR SDR SDR DDR
3
Internal
Sampling
Internal DQS Internal
Sampling
Internal DQS Internal
Sampling
External DQS
N1 PAD
Loopback
Internal
Loopback
N1 PAD
Loopback
Internal
Loopback
N1 Extrenal DQS
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
SCK Duty Cycle t
SDC
ns
tSCK/2 - 1.5
tSCK/2 + 1.5
tSCK/2 - 1.5
tSCK/2 + 1.5
tSCK/2 - 1.5
tSCK/2 + 1.5
tSCK/2 - 1.5
tSCK/2 + 1.5
tSCK/2 - 0.750 tSCK/2 - 0.750
tSCK/2 - 1.5
tSCK/2 + 1.5
tSCK/2 - 2.5
tSCK/2 + 2.5
tSCK/2 - 2.5
tSCK/2 + 2.5
Data Input Setup Time t
IS
ns 15 - 2.5 - 10 - 14 - 1.5 - 9 - 25 - -2 -
Data Input Hold Time t
IH
ns 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 -
Data Output Valid Time t
OV
ns - 4.5 - 4.5 - 4.5 - 4 - 4 - 4 - 10 - 10
Data Output In-Valid
Time
t
IV
ns 5 - 5 - 5 - 5 - 3
5
- 5 - 5 - 5 -
CS to SCK Time
6
t
CSSCK
ns 5 - 5 - 5 - 5 - 5 - 5 - 10 - 10 -
SCK to CS Time
7
t
SCKCS
ns 5 - 5 - 5 - 5 - 5 - 5 - 5 - 5 -
Output Load pf 25 25 25 25 25 25 25 25
1. See Reference Manual for details on mode settings
2. See Reference Manual for details on mode settings
3. Valid for HyperRAM only
4. RWDS(External DQS CLK) frequency
5. For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.
6. Program register value QuadSPI_FLSHCR[TCSS] = 4`h2
7. Program register value QuadSPI_FLSHCR[TCSH] = 4`h1
Memory and memory interfaces
S32K1xx Data Sheet, Rev. 4, 06/2017
32
Preliminary
NXP Semiconductors