Datasheet

Table 23. QuadSPI electrical specifications
FLASH PORT Sym Unit FLASH A FLASH B
RUN
1
HSRUN
1
RUN/HSRUN
2
QuadSPI Mode SDR SDR SDR DDR
3
Internal
Sampling
Internal DQS Internal
Sampling
Internal DQS Internal
Sampling
External DQS
N1 PAD
Loopback
Internal
Loopback
N1 PAD
Loopback
Internal
Loopback
N1 Extrenal DQS
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Register Settings
MCR[DDR_EN] - 0 0 0 0 0 0 0 1
MCR[DQS_EN] - 0 1 1 0 1 1 0 1
MCR[SCLKCFG[0]] - - 1 0 - 1 0 - -
MCR[SCLKCFG[1]] - - 1 0 - 1 0 - -
MCR[SCLKCFG[2]] - - - - - - - - 0
MCR[SCLKCFG[3]] - - - - - - - - 0
MCR[SCLKCFG[5]] - - - - - - - - 1
SMPR[FSPHS] - 0 1 0 0 1 0 0 0
SMPR[FSDLY] - 0 0 0 0 0 0 0 0
SOCCR
[SOCCFG[7:0]]
- 0 23 - 0 30 - -
SOCCR[SOCCFG[15:8]] - - - - - - - - 30
FLSHCR[TDH] - 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01
Timing Parameters
SCK Clock Frequency f
SCK
MHz - 38 - 64 - 48 - 40 - 80 - 50 - 20 - 20
4
SCK Clock Period t
SCK
ns
1/fSCK
-
1/fSCK
-
1/fSCK
-
1/fSCK
-
1/fSCK
-
1/fSCK
- 50.0 - 50.0
4
-
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Memory and memory interfaces
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
31