Datasheet

6.2.4 Low Power Oscillator (LPO) electrical specifications
Table 19. Low Power Oscillator (LPO) electrical specifications
Symbol Parameter Min. Typ. Max. Unit
F
LPO
Internal low power oscillator frequency 113 128 139 kHz
T
startup
Startup Time — — 20 µs
6.2.5 SPLL electrical specifications
Table 20. SPLL electrical specifications
Symbol Parameter Min. Typ. Max. Unit
F
SPLL_REF
1
PLL Reference Frequency Range 8 — 16 MHz
F
SPLL_Input
2
PLL Input Frequency 8 — 40 MHz
F
VCO_CLK
VCO output frequency 180 — 320 MHz
F
SPLL_CLK
PLL output frequency 90 — 160 MHz
J
CYC_SPLL
PLL Period Jitter (RMS)
3
at F
VCO_CLK
180 MHz — 120 — ps
at F
VCO_CLK
320 MHz — 75 — ps
J
ACC_SPLL
PLL accumulated jitter over 1µs (RMS)
3
at F
VCO_CLK
180 MHz — 1350 — ps
at F
VCO_CLK
320 MHz — 600 — ps
D
UNL
Lock exit frequency tolerance ± 4.47 — ± 5.97 %
T
SPLL_LOCK
Lock detector detection time
4
— — 150 × 10
-6
+
1075(1/F
SPLL_REF
)
s
1. F
SPLL_REF
is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG
register of Reference Manual.
2. F
SPLL_Input
is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input
source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass
mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.
3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
PCB and results will vary
4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.
Memory and memory interfaces
6.3.1
Flash memory module (FTFC) electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.3
Memory and memory interfaces
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
27