Datasheet

Table 15. External System Oscillator electrical specifications
(continued)
Symbol Description Min. Typ. Max. Unit Notes
High-gain mode (HGO=1) — 1 — MΩ
R
S
Series resistor
Low-gain mode (HGO=0) — 0 — kΩ
High-gain mode (HGO=1) — 0 — kΩ
V
pp
Peak-to-peak amplitude of oscillation (oscillator mode) 3
Low-gain mode (HGO=0) — 1.0 — V
High-gain mode (HGO=1) — 3.3 — V
1. Crystal oscillator circuit provides stable oscillations when g
mXOSC
> 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * ESR * (2πF)
2
* (C
0
+ C
L
)
2
where:
• g
mXOSC
is the transconductance of the internal oscillator circuit
• ESR is the equivalent series resistance of the external crystal
• F is the external crystal oscillation frequency
• C
0
is the shunt capacitance of the external crystal
• C
L
is the external crystal total load capacitance. C
L
= C
s
+ [C
1
*C
2
/(C
1
+C
2
)]
• C
s
is stray or parasitic capacitance on the pin due to any PCB traces
• C
1
, C
2
external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values
2.
• When low-gain is selected, internal R
F
will be selected and external R
F
should not be attached.
• When high-gain is selected, external R
F
(1 M Ohm) needs to be connected for proper operation of the crystal. For
external resistor, up to 5% tolerance is allowed.
3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.2.2 External System Oscillator frequency specifications
Table 16. External System Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
f
osc_hi
Oscillator crystal or resonator frequency 4 — 40 MHz
f
ec_extal
Input clock frequency (external clock mode) — — 50 MHz
t
dc_extal
Input clock duty cycle (external clock mode) 40 50 60 %
t
cst
Crystal Start-up Time
8 MHz low-gain mode (HGO=0) — 1.5 — ms 1
8 MHz high-gain mode (HGO=1) — 2.5 —
40 MHz low-gain mode (HGO=0) — 2 —
40 MHz high-gain mode (HGO=1) — 2 —
1. Proper PC board layout procedures must be followed to achieve specifications.
Clock interface modules
S32K1xx Data Sheet, Rev. 4, 06/2017
NXP Semiconductors
Preliminary
25