Datasheet

4.7.1 Modes configuration
Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes used in
gathering the power consumption data stated in the above table Table 7. For full
functionality refer to table: Module operation in available low power modes of the
Reference Manual.
4.8 ESD handling ratings
Symbol Description Min. Max. Unit Notes
V
HBM
Electrostatic discharge voltage, human body model − 4000 4000 V 1
V
CDM
Electrostatic discharge voltage, charged-device model 2
All pins except the corner pins − 500 500 V
Corner pins only − 750 750 V
I
LAT
Latch-up current at ambient temperature of 125 °C − 100 100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.9 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
I/O parameters
5.1
AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
5
I/O parameters
S32K1xx Data Sheet, Rev. 4, 06/2017
18
Preliminary
NXP Semiconductors