Datasheet

Table 5. V
DD
supply LVR, LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
V
LVD
Falling low-voltage detect threshold 2.8 2.875 3 V
V
LVD_HYST
LVD hysteresis — 50 — mV 1
V
LVW
Falling low-voltage warning threshold 4.19 4.305 4.5 V
V
LVW_HYST
LVW hysteresis — 75 — mV 1
V
BG
Bandgap voltage reference 0.97 1.00 1.03 V
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
4.6 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration:
• RUN Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• HSRUN Mode:
• Clock source: SPLL
• SYS_CLK/CORE_CLK = 112 MHz
• BUS_CLK = 56 MHz
• FLASH_CLK = 28 MHz
• VLPR Mode:
• Clock source: SIRC
• SYS_CLK/CORE_CLK = 4 MHz
• BUS_CLK = 4 MHz
• FLASH_CLK = 1 MHz
• STOP1/STOP2 Mode:
• Clock source: FIRC
• SYS_CLK/CORE_CLK = 48 MHz
• BUS_CLK = 48 MHz
• FLASH_CLK = 24 MHz
• VLPS Mode: All clock sources disabled.
Table 6. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit
t
POR
After a POR event, amount of time from the point V
DD
reaches 2.7 V to execution of the first instruction
across the operating temperature range of the chip.
— 325 — μs
Table continues on the next page...
General
S32K1xx Data Sheet, Rev. 4, 06/2017
14
Preliminary
NXP Semiconductors