Datasheet
4.4 Power and ground pins
VDD
VDDA
VREFH
VREFL
VSSA/VSS
VDD
VSS
VDD
VSS
VSS
VDD
100 LQFP
Package
VDD
VSS
VDDA
VREFH
VREFL / VSSA/VSS
64 LQFP
Package
C
DEC
C
REF
C
REF
C
DEC
C
DEC
C
DEC
C
DEC
C
DEC
C
DEC
VDD
VSS
VSS
VDD
144 LQFP
Package
C
DEC
C
DEC
VDD
VSS
VDD
VSS
VSS
VDD
176 LQFP
Package
C
DEC
C
DEC
C
DEC
VDD
VSS
C
DEC
VSS
VDD
C
DEC
VDD
VSS
C
DEC
VDD
VSS
C
DEC
VSS
VDD
C
DEC
VDD
VDDA
VREFH
VREFL
VSS
C
DEC
C
REF
C
DEC
VDD
VSS
C
DEC
VSSA/VSS
VDD
C
DEC
VDD
VDDA
VREFH
VREFL
VSS
C
DEC
C
REF
C
DEC
VDD
VSS
C
DEC
VSSA/VSS
Figure 5. Pinout decoupling
Table 4. Supplies decoupling capacitors 1, 2
Symbol Description Min.
3
Typ. Max. Unit
C
REF
, 4
,
5
ADC reference high decoupling capacitance 70 100 — nF
C
DEC
5
,
6
,
7
Recommended decoupling capacitance 70 100 — nF
1. V
DD
and V
DDA
must be shorted to a common source on PCB. Appropriate decoupling capacitors to be used to filter noise
on the supplies. See application note AN5032 for reference supply design for SAR ADC. All V
SS
pins should be connected
to common ground at the PCB level.
2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
3. Minimum recommendation is after considering component aging and tolerance.
4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
6. Contact your local Field Applications Engineer for details on best analog routing practices.
7. The filtering used for decoupling the device supplies must comply with the following best practices rules:
• The protection/decoupling capacitors must be on the path of the trace connected to that component.
General
S32K1xx Data Sheet, Rev. 4, 06/2017
12
Preliminary
NXP Semiconductors