Datasheet

Appendix A Electrical Characteristics
MC9S08DZ60 Series Data Sheet, Rev. 4
384 Freescale Semiconductor
Figure A-3. Active Background Debug Mode Latch Timing
Figure A-4. Pin Interrupt Timing
A.12.2 Timer/PWM
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table A-14. TPM Input Timing
Num C Rating Symbol Min Max Unit
1 — External clock frequency
f
TCLK
dc
f
Bus
/4
MHz
2 — External clock period
t
TCLK
4—
t
cyc
3 D External clock high time
t
clkh
1.5 —
t
cyc
4 D External clock low time
t
clkl
1.5 —
t
cyc
5 D Input capture pulse width
t
ICPW
1.5 —
t
cyc
BKGD/MS
RESET
t
MSSU
t
MSH
t
IHIL
PIAx/PIBx/PIDx
t
ILIH
IRQ/PIAx/PIBx/PIDx