Datasheet

Appendix A Electrical Characteristics
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor 383
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Figure A-2. Reset Timing
Table A-13. Control Timing
Nu
m
C Rating Symbol Min Typical
1
1
Typical data was characterized at 5.0 V, 25°C unless otherwise stated.
Max Unit
1
D/
P
Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 20 MHz
2 T Internal low-power oscillator period
t
LPO
— 1500 — μs
3D
External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
t
extrst
1.5 x t
cyc
—ns
4D
Reset low drive
3
3
When any reset is initiated, internal circuitry drives the RESET pin low for about 34 cycles of t
cyc
. After POR reset, the bus
clock frequency changes to the untrimmed DCO frequency (freset = (f
dco_ut
)/4) because TRIM is reset to 0x80 and FTRIM is
reset to 0; and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets, trim stays at the pre-reset value.
t
rstdrv
34 x t
cyc
—ns
5 D Active background debug mode latch setup time
t
MSSU
25 — ns
6 D Active background debug mode latch hold time
t
MSH
25 — ns
7D
IRQ/PIAx/ PIBx/PIDx pulse width
Asynchronous path
2
Synchronous path
3
t
ILIH,
t
IHIL
100
1.5 t
cyc
——ns
8T
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)
4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
4
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40°C to 125°C.
t
Rise
, t
Fall
—
—
40
75
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise
, t
Fall
—
—
11
35
ns
t
extrst
RESET PIN