Datasheet

Chapter 16 Timer/PWM Module (S08TPMV3)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor 345
Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset
Figure 0-2. Generation of low-true EPWM signal by TPM v2 and v3 after the reset
The following procedure can be used in TPM v3 (when the channel pin is also a port pin) to emulate
the high-true EPWM generated by TPM v2 after the reset.
ELSnB:ELSnA BITS
CLKSB:CLKSA BITS
0
TPMxMODH:TPMxMODL = 0x0007
TPMxCnVH:TPMxCnVL = 0x0005
TPMxCNTH:TPMxCNTL
TPMv2 TPMxCHn
EPWM mode
00
00 10
BUS CLOCK
01
1234567012
CHnF BIT
MSnB:MSnA BITS
00 10
(in TPMv2 and TPMv3)
TPMv3 TPMxCHn
...
RESET (active low)
ELSnB:ELSnA BITS
CLKSB:CLKSA BITS
0
TPMxMODH:TPMxMODL = 0x0007
TPMxCnVH:TPMxCnVL = 0x0005
TPMxCNTH:TPMxCNTL
TPMv2 TPMxCHn
EPWM mode
00
00 01
BUS CLOCK
01
1234567012
CHnF BIT
MSnB:MSnA BITS
00 10
(in TPMv2 and TPMv3)
TPMv3 TPMxCHn
...
RESET (active low)