Datasheet

Chapter 16 Timer/PWM Module (S08TPMV3)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor 333
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
0 00 01 Input capture Capture on rising edge
only
10 Capture on falling edge
only
11 Capture on rising or
falling edge
01 01 Output compare Toggle output on
compare
10 Clear output on
compare
11 Set output on compare
1X 10 Edge-aligned
PWM
High-true pulses (clear
output on compare)
X1 Low-true pulses (set
output on compare)
1 XX 10 Center-aligned
PWM
High-true pulses (clear
output on compare-up)
X1 Low-true pulses (set
output on compare-up)
76543210
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset 00000000
Figure 16-13. TPM Channel Value Register High (TPMxCnVH)
76543210
R
Bit 7 654321Bit 0
W
Reset 00000000
Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)
Table 16-6. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration