Datasheet

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ60 Series Data Sheet, Rev. 4
250 Freescale Semiconductor
Section 12.3.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only
read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Read: Anytime when TXEx flag is set (see Section 12.3.6, “MSCAN Transmitter Flag Register
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.10,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Write: Unimplemented
12.5 Functional Description
12.5.1 General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
76543210
R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8
W
Reset: xxxxxxxx
Figure 12-36. Time Stamp Register — High Byte (TSRH)
76543210
R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0
W
Reset: xxxxxxxx
Figure 12-37. Time Stamp Register — Low Byte (TSRL)