Datasheet

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ60 Series Data Sheet, Rev. 4
244 Freescale Semiconductor
Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only
when RXF flag is set (see Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”).
Write: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.6, “MSCANTransmitterFlag
Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 12.3.10, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). Unimplemented for
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
12.4.1 Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
12.4.1.1 IDR0–IDR3 for Extended Identifier Mapping
Register
Name
Bit 7 654321Bit 0
IDR0
R
ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3
W
IDR1
R
ID2 ID1 ID0 RTR
1
1
The position of RTR differs between extended and standard indentifier mapping.
IDE
2
2
IDE is 0.
W
IDR2
R
W
IDR3
R
W
= Unused, always read ‘x’
Figure 12-24. Receive/Transmit Message Buffer — Standard Identifier Mapping
76543210
R
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
W
Reset: xxxxxxxx
Figure 12-25. Identifier Register 0 (IDR0) — Extended Identifier Mapping