Datasheet

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DZ60 Series Data Sheet, Rev. 4
222 Freescale Semiconductor
12.1.3 Block Diagram
Figure 12-2. MSCAN Block Diagram
12.2 External Signal Description
The MSCAN uses two external pins:
12.2.1 RXCAN — CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
12.2.2 TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
0 = Dominant state
1 = Recessive state
12.2.3 CAN System
A typical CAN system with MSCAN is shown in Figure 12-3. Each CAN node is connected physically to
the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective nodes.
RXCAN
TXCAN
Receive/
Transmit
Engine
Message
Filtering
and
Buffering
Control
and
Status
Wake-Up Interrupt Req.
Errors Interrupt Req.
Receive Interrupt Req.
Transmit Interrupt Req.
CANCLK
Bus Clock
Configuration
Oscillator Clock
MUX Presc.
Tq Clk
MSCAN
Low Pass Filter
Wake-Up
Registers