Datasheet
Chapter 6 Parallel Input/Output Control
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor 105
6.5.5 Port E Registers
Port E is controlled by the registers listed below.
6.5.5.1 Port E Data Register (PTED)
6.5.5.2 Port E Data Direction Register (PTEDD)
76543210
R
PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1
1
1
Reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit.
PTED0
W
Reset: 00000000
Figure 6-32. Port E Data Register (PTED)
Table 6-30. PTED Register Field Descriptions
Field Description
7:0
PTED[7:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
76543210
R
PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1
1
1
PTEDD1 has no effect on the input-only PTE1 pin.
PTEDD0
W
Reset: 00000000
Figure 6-33. Port E Data Direction Register (PTEDD)
Table 6-31. PTEDD Register Field Descriptions
Field Description
7:0
PTEDD[7:0]
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.