Datasheet

PEMD3_PIMD3_PUMD3_10 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 10 — 15 November 2009 3 of 11
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors; R1 = 10 kΩ, R2 = 10 kΩ
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Device mounted on an FR4 PCB with 65 μm copper strip line, standard footprint.
[3] Reflow soldering is the only recommended soldering method.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor; for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter - 50 V
V
CEO
collector-emitter voltage open base - 50 V
V
EBO
emitter-base voltage open collector - 10 V
V
I
input voltage TR1
positive - +40 V
negative - −10 V
input voltage TR2
positive - +10 V
negative - −40 V
I
O
output current (DC) - 100 mA
I
CM
peak collector current - 100 mA
P
tot
total power dissipation T
amb
≤ 25 °C
SOT363
[1]
-200mW
SOT457
[2]
-300mW
SOT666
[1][3]
-200mW
T
stg
storage temperature −65 +150 °C
T
j
junction temperature - 150 °C
T
amb
ambient temperature −65 +150 °C
Per device
P
tot
total power dissipation T
amb
≤ 25 °C
SOT363
[1]
-300mW
SOT457
[2]
-600mW
SOT666
[1][3]
-300mW