Datasheet

Philips Semiconductors

PCF8563

Real time clock/calendar

Product data Rev. 04 — 12 March 2004 7 of 30

9397 750 12999

8.6.1 Control/status 1 register

8.6.2 Control/status 2 register

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten by

software. If both timer and alarm interrupts are required in the application, the source

of the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt

when TF or AF is asserted, respectively. The interrupt is the logical OR of these two

conditions when both AIE and TIE are set.

Table 6: Control/status 1 (address 00H) bits description

Bit Symbol Value Description

7 TEST1 0 normal mode

1 EXT_CLK test mode

6 0 default value is logic 0

5 STOP 0 RTC source clock runs

1 all RTC divider chain ﬂip-ﬂops are asynchronously set to logic 0; the RTC clock is

stopped (CLKOUT at 32.768 kHz is still available)

4 0 default value is logic 0

3 TESTC 0 Power-on reset override facility is disabled; set to logic 0 for normal operation

1 Power-on reset override may be enabled

2 to 0 0 default value is logic 0

Table 7: Control/status 2 (address 01H) bits description

Bit Symbol Value Description

7 to 5 0 default value is logic 0

4 TI/TP 0

INT is active when TF is active (subject to the status of TIE)

INT pulses active according to Table 8 (subject to the status of TIE); note that if

AF and AIE are active then

INT will be permanently active

3 AF 0 (read) alarm ﬂag inactive

1 (read) alarm ﬂag active

0 (write) alarm ﬂag is cleared

1 (write) alarm ﬂag remains unchanged

2 TF 0 (read) timer ﬂag inactive

1 (read) timer ﬂag active

0 (write) timer ﬂag is cleared

1 (write) timer ﬂag remains unchanged

1 AIE 0 alarm interrupt disabled

1 alarm interrupt enabled

0 TIE 0 timer interrupt disabled

1 timer interrupt enabled